pulp-platform / clintLinks
RISC-V Core Local Interrupt Controller (CLINT)
☆30Updated 3 weeks ago
Alternatives and similar repositories for clint
Users that are interested in clint are comparing it to the libraries listed below
Sorting:
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Platform Level Interrupt Controller☆44Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- ☆126Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- ☆42Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated 2 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- ☆113Updated 2 months ago
- AIA IP compliant with the RISC-V AIA spec☆46Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆111Updated 4 months ago
- Scalable Interface for RISC-V ISA Extensions☆23Updated this week
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆27Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- An implementation of RISC-V☆47Updated last month
- RISC-V Nox core☆71Updated 6 months ago
- ☆33Updated 2 months ago
- ☆51Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- The purpose of the repo is to support CORE-V Wally architectural verification☆17Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆56Updated last week
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 2 months ago