pulp-platform / clintLinks
RISC-V Core Local Interrupt Controller (CLINT)
☆29Updated last week
Alternatives and similar repositories for clint
Users that are interested in clint are comparing it to the libraries listed below
Sorting:
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Platform Level Interrupt Controller☆43Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- AIA IP compliant with the RISC-V AIA spec☆45Updated 9 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆106Updated last month
- ☆42Updated 3 years ago
- ☆105Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Advanced Architecture Labs with CVA6☆70Updated last year
- RISC-V Nox core☆68Updated 3 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- Simple UVM environment for experimenting with Verilator.☆28Updated last week
- DUTH RISC-V Microprocessor☆22Updated 11 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆18Updated 7 months ago
- ☆50Updated last month
- ☆30Updated 3 weeks ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 3 months ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated last month