Alternatives and similar repositories for muntjac-soc

Users that are interested in muntjac-soc are comparing it to the libraries listed below

• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆31Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• chipsalliance / tilelink
  ☆30Updated 5 months ago
• pulp-platform / redmule
  ☆61Updated 2 weeks ago
• pulp-platform / axi_llc
  ☆27Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆56Updated 3 months ago
• chipsalliance / espresso
  ☆39Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated this week
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆26Updated last year
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆33Updated last month
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆33Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆37Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆42Updated this week
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆41Updated 2 years ago
• tenstorrent / rv-core-dv-kit
  ☆25Updated 2 months ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆47Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆99Updated last month
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆66Updated 3 weeks ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆63Updated 11 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆145Updated 6 months ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆29Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 6 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated last week
• riscv-software-src / riscof
  ☆78Updated last month
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago