riscv-non-isa / riscv-ras-eriView external linksLinks
The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors, and configuration.
☆10Feb 6, 2026Updated last week
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