100 MB/s Ethernet MAC Layer Switch
☆15Jul 17, 2014Updated 11 years ago
Alternatives and similar repositories for mac_layer_switch
Users that are interested in mac_layer_switch are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Ethernet Switch (layer 2)☆57Oct 18, 2023Updated 2 years ago
- 1G eth UDP / IP Stack☆10Jul 17, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆35Sep 17, 2019Updated 6 years ago
- ☆29May 11, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AES☆15Oct 4, 2022Updated 3 years ago
- An Ethernet MAC conforming to IEEE 802.3☆24May 13, 2017Updated 9 years ago
- Mirror of GNU FreeIPMI Git Repo - http://savannah.gnu.org/projects/freeipmi/. I maintain the upstream of FreeIPMI and can accept Github …☆13Jun 1, 2026Updated last week
- Ethernet 10GE MAC☆47Jul 17, 2014Updated 11 years ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- ☆12Dec 28, 2022Updated 3 years ago
- The developed solution for designing an affordable manipulator to be used for teaching proposes where students get to use an FPGA and the…☆11Oct 3, 2023Updated 2 years ago
- Ethernet MAC for the Digilent Nexys 4 DDR FPGA.☆31Aug 21, 2018Updated 7 years ago
- AHB DMA 32 / 64 bits☆62Jul 17, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FOC in FPGA implementation using MATLAB Simulink VDH code generation☆16Jul 3, 2020Updated 5 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆24Jul 17, 2014Updated 11 years ago
- Ethernet MAC 10/100 Mbps☆87Oct 2, 2019Updated 6 years ago
- Ethernet switch implementation written in Verilog☆65Jun 13, 2023Updated 2 years ago
- An OpenFlow implementation for the NetFPGA-10G card☆19Feb 18, 2015Updated 11 years ago
- AXI DMA 32 / 64 bits☆129Jul 17, 2014Updated 11 years ago
- ☆18Nov 4, 2024Updated last year
- Mini RISC-V CPU☆11Dec 26, 2019Updated 6 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Hardware Assisted IEEE 1588 IP Core☆30Jul 17, 2014Updated 11 years ago
- Precise Point Positioning Library☆11Dec 2, 2020Updated 5 years ago
- xilinx的zynq开源硬件和软件☆19Aug 11, 2020Updated 5 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 5 years ago
- Wishbone SATA Controller☆26Oct 16, 2025Updated 7 months ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- ☆27Jun 12, 2022Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆18Nov 10, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 7 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 10 years ago
- FPGA implementation of Real-time Ethernet communication using RMII Interface☆14Sep 18, 2014Updated 11 years ago