freecores / mac_layer_switchLinks
100 MB/s Ethernet MAC Layer Switch
☆15Updated 11 years ago
Alternatives and similar repositories for mac_layer_switch
Users that are interested in mac_layer_switch are comparing it to the libraries listed below
Sorting:
- Generic AXI to AHB bridge☆18Updated 11 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- UART -> AXI Bridge☆70Updated 4 years ago
- APB to I2C☆43Updated 11 years ago
- ☆38Updated 10 years ago
- I2C controller core☆48Updated 3 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆48Updated 9 years ago
- Reed Solomon Decoder (204,188)☆12Updated 11 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Updated last month
- ☆80Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated 2 years ago
- AHB DMA 32 / 64 bits☆59Updated 11 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Updated 6 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 4 months ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- Verification IP for APB protocol☆75Updated 5 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Updated 4 years ago