freecores / mac_layer_switchLinks
100 MB/s Ethernet MAC Layer Switch
☆15Updated 10 years ago
Alternatives and similar repositories for mac_layer_switch
Users that are interested in mac_layer_switch are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆61Updated 4 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- ☆36Updated 9 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- I2C controller core☆47Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- ☆69Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆37Updated 4 years ago
- AHB3-Lite Interconnect☆89Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- ☆71Updated 3 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆69Updated 5 years ago
- APB to I2C☆42Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆15Updated 2 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Verilog I2C Slave☆23Updated 10 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- AXI Interconnect☆50Updated 3 years ago