freecores / mac_layer_switch
100 MB/s Ethernet MAC Layer Switch
☆14Updated 10 years ago
Alternatives and similar repositories for mac_layer_switch:
Users that are interested in mac_layer_switch are comparing it to the libraries listed below
- Implementation of the PCIe physical layer☆33Updated last month
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- Generic AXI to AHB bridge☆16Updated 10 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆31Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆61Updated last year
- ☆17Updated 3 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆21Updated 7 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆13Updated 2 years ago
- ☆14Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 9 months ago
- ☆35Updated 9 years ago
- ☆20Updated 5 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆24Updated 6 years ago
- Verilog I2C Slave☆23Updated 10 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 6 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- ☆24Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆47Updated 2 years ago