Alternatives and similar repositories for bootloader_recovery

Users that are interested in bootloader_recovery are comparing it to the libraries listed below

• starfive-tech / JH7100_ddrinit
  ☆16Updated 3 years ago
• starfive-tech / JH7100_secondBoot
  ☆14Updated 3 years ago
• kprasadvnsi / JH71xx-tools
  Bootloader recovery and updater tool for StarFive JH71x0 SoCs.
  ☆15Updated 3 years ago
• sifiveinc / meta-sifive
  SiFive OpenEmbedded / Yocto BSP Layer
  ☆54Updated 3 weeks ago
• starfive-tech / opensbi
  ☆18Updated 2 weeks ago
• riscv-non-isa / riscv-brs
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…
  ☆54Updated this week
• starfive-tech / Fedora_on_StarFive
  ☆63Updated 2 years ago
• riscv-non-isa / riscv-device-tree-doc
  RISC-V Specific Device Tree Documentation
  ☆42Updated last year
• riscv-admin / riscv-uefi-edk2-docs
  Documentation and status of UEFI on RISC-V
  ☆63Updated 4 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated last year
• antmicro / renode-beagle-v
  ☆12Updated last year
• beagleboard / beaglev-starlight
  ☆81Updated 4 years ago
• Wren6991 / ChristmasSoC
  Dual-core RISC-V SoC with JTAG, atomics, SDRAM
  ☆25Updated 3 years ago
• pine64 / bl602-re
  Reverse engineering of BL602 blobs
  ☆100Updated 2 years ago
• polarfire-soc / meta-polarfire-soc-yocto-bsp
  This repository is no longer maintained and will be archived, please see https://github.com/linux4microchip/meta-mchp
  ☆58Updated 3 months ago
• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 3 years ago
• riscv-non-isa / riscv-uefi
  ☆33Updated 3 years ago
• sipeed / bl602-hal
  Hardware Abstract Layer for BL602 RISC-V WiFi + BLE SoC in embedded Rust
  ☆78Updated last year
• prjunnamed / prjcombine
  An FPGA reverse engineering and documentation project
  ☆58Updated 2 weeks ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated 3 weeks ago
• tomtor / rust-litex
  Running Rust on the (Linux) Litex VexRiscv FPGA SOC
  ☆14Updated 4 months ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆63Updated this week
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆14Updated 3 weeks ago
• westerndigitalcorporation / libmctp
  libMCTP is a MCTP (Management Component Transport Protocol) implementation for Rust.
  ☆15Updated 7 months ago
• starfive-tech / freelight-u-sdk
  ☆28Updated 3 years ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• SoCFPGA-learning / Chameleon96
  The Chameleon96™ board, based on Intel® Cyclone V SoC FPGA
  ☆15Updated last year
• pine64 / bl602-docs
  Documentation of the BL602 IC
  ☆65Updated 2 years ago
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated 2 years ago
• riscv / virtual-memory
  ☆39Updated 4 years ago