Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
☆1,589Apr 15, 2026Updated last month
Alternatives and similar repositories for learn
Users that are interested in learn are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,517Nov 18, 2025Updated 6 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆163Feb 2, 2026Updated 3 months ago
- RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.☆351Apr 2, 2026Updated last month
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆531May 10, 2026Updated last week
- Self checking RISC-V directed tests☆119Jun 3, 2025Updated 11 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V XV6/Linux SoC, marchID: 0x2b☆1,085Mar 3, 2026Updated 2 months ago
- RISC-V Instruction Set Manual☆4,618May 15, 2026Updated last week
- RISC-V Nox core☆72Jul 22, 2025Updated 10 months ago
- Spike, a RISC-V ISA Simulator☆3,115Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆146Oct 2, 2025Updated 7 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆128Dec 17, 2023Updated 2 years ago
- ☆485Apr 25, 2026Updated 3 weeks ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Nov 16, 2023Updated 2 years ago
- SERV - The SErial RISC-V CPU☆1,801Feb 19, 2026Updated 3 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,149Jun 27, 2024Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆238May 12, 2026Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆114Apr 22, 2026Updated last month
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆870Updated this week
- RISC-V Opcodes☆853Updated this week
- CORE-V Family of RISC-V Cores☆352Mar 31, 2026Updated last month
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,061May 14, 2026Updated last week
- List of awesome open source hardware tools, generators, and reusable designs☆2,335Mar 2, 2026Updated 2 months ago
- Open-source implementations of reference Physical True Random Number Generators (TRNG or PTRNG) based on ring oscillators.☆17Mar 26, 2026Updated last month
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,875May 7, 2026Updated 2 weeks ago
- A graphical processor simulator and assembly editor for the RISC-V ISA☆3,313May 12, 2026Updated last week
- GNU toolchain for RISC-V, including GCC☆4,496Updated this week
- ☆1,189May 1, 2026Updated 3 weeks ago
- RISC-V Architecture Profiles☆186Apr 22, 2026Updated last month
- RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-…☆651Jan 4, 2024Updated 2 years ago
- A pipelined RISC-V processor☆64Dec 1, 2023Updated 2 years ago
- RISC-V Assembly Programmer's Manual☆1,629Apr 29, 2026Updated 3 weeks ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆28Oct 31, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,939May 13, 2026Updated last week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,553May 12, 2026Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆155Updated this week
- 3-stage RV32IMACZb* processor with debug☆1,052Apr 23, 2026Updated 3 weeks ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆509Jul 18, 2025Updated 10 months ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 3 months ago
- 32-bit Superscalar RISC-V CPU☆1,248Sep 18, 2021Updated 4 years ago