asinghani / open-eda-course
Curriculum for a university course to teach chip design using open source EDA tools
☆62Updated last year
Alternatives and similar repositories for open-eda-course:
Users that are interested in open-eda-course are comparing it to the libraries listed below
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆73Updated this week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆66Updated 4 years ago
- Home of the open-source EDA course.☆35Updated last month
- ☆40Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆58Updated last year
- ☆14Updated 2 years ago
- ☆75Updated 3 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆13Updated last week
- Solve one design problem each day for a month☆40Updated 2 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated last month
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆152Updated 2 weeks ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆40Updated 3 years ago
- ☆12Updated 2 weeks ago
- ☆31Updated 3 months ago
- ☆10Updated 2 years ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Static Timing Analysis Full Course☆52Updated 2 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆81Updated 7 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago