asinghani / open-eda-courseLinks
Curriculum for a university course to teach chip design using open source EDA tools
☆112Updated 2 years ago
Alternatives and similar repositories for open-eda-course
Users that are interested in open-eda-course are comparing it to the libraries listed below
Sorting:
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆91Updated last year
- Introductory course into static timing analysis (STA).☆99Updated 4 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆80Updated 4 years ago
- SystemVerilog Tutorial☆180Updated 2 weeks ago
- This repo provide an index of VLSI content creators and their materials☆160Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆126Updated last month
- ☆15Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆43Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆14Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆115Updated last year
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆193Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆151Updated this week
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- Static Timing Analysis Full Course☆62Updated 2 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆29Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆19Updated 4 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆30Updated 2 months ago
- ☆168Updated 3 years ago
- ☆14Updated 3 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆168Updated 3 months ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆22Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆101Updated 2 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆14Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago