stevehoover / LF-Building-a-RISC-V-CPU-Core

Related projects: ⓘ

• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,375Updated 3 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆597Updated 2 weeks ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆280Updated 3 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆840Updated 3 years ago
• riscv / learn
  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
  ☆490Updated 2 months ago
• riscv-non-isa / riscv-arch-test
  ☆501Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆810Updated last year
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆619Updated 9 months ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆566Updated 2 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆237Updated this week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆165Updated 2 years ago
• riscv-software-src / riscv-tests
  ☆873Updated 2 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,338Updated this week
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆324Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆926Updated 2 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆626Updated last month
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆787Updated this week
• mattvenn / awesome-opensource-asic-resources
  ☆278Updated last year
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆376Updated last year
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆480Updated last year
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆387Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆425Updated 2 weeks ago
• drom / awesome-hdl
  Hardware Description Languages
  ☆937Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆357Updated last week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆812Updated 2 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆350Updated last month
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆223Updated 3 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆199Updated 7 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆535Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆997Updated 3 weeks ago