Alternatives and similar repositories for LF-Building-a-RISC-V-CPU-Core

Users that are interested in LF-Building-a-RISC-V-CPU-Core are comparing it to the libraries listed below

• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆450Updated last week
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆278Updated 10 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆433Updated 3 years ago
• mattvenn / awesome-opensource-asic-resources
  ☆364Updated 2 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆748Updated last month
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆470Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆624Updated last month
• riscv-non-isa / riscv-arch-test
  ☆614Updated last week
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆402Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆145Updated 5 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 8 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆746Updated 2 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,139Updated 4 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆278Updated 6 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆366Updated 9 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆678Updated 4 months ago
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆734Updated 10 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆332Updated last year
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,704Updated last month
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆143Updated 2 months ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆667Updated last week
• martinKindall / risc-v-single-cycle
  A Single Cycle Risc-V 32 bit CPU
  ☆54Updated 2 months ago
• RISCV-MYTH-WORKSHOP / RISC-V-CPU-Core-using-TL-Verilog
  risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom
  ☆15Updated 5 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆310Updated 10 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆680Updated 2 weeks ago
• riscvarchive / educational-materials
  Educational materials for RISC-V
  ☆225Updated 4 years ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆455Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,151Updated 6 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆150Updated 6 years ago