Alternatives and similar repositories for LF-Building-a-RISC-V-CPU-Core

Users that are interested in LF-Building-a-RISC-V-CPU-Core are comparing it to the libraries listed below

• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆408Updated last week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆194Updated 3 years ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆257Updated 8 months ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆655Updated this week
• mattvenn / awesome-opensource-asic-resources
  ☆346Updated 2 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated 5 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆592Updated 2 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆589Updated 3 weeks ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆730Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆734Updated 3 weeks ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆268Updated 3 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆392Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆453Updated 3 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆270Updated 4 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆294Updated 7 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 9 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,094Updated 4 years ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆141Updated 3 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,641Updated 3 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated 2 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆375Updated 2 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆425Updated 2 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆405Updated 8 months ago
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆214Updated 6 months ago
• riscv / learn
  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
  ☆1,017Updated 2 weeks ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆725Updated 7 months ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆79Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆665Updated 2 months ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆126Updated 4 years ago