Alternatives and similar repositories for LF-Building-a-RISC-V-CPU-Core

Users that are interested in LF-Building-a-RISC-V-CPU-Core are comparing it to the libraries listed below

• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,041Updated 3 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆389Updated this week
• riscv-non-isa / riscv-arch-test
  ☆567Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆559Updated 3 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆259Updated 2 months ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆224Updated 5 months ago
• riscv-software-src / riscv-tests
  ☆1,024Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆711Updated last month
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆920Updated 7 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆709Updated last month
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆642Updated 3 weeks ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆191Updated 3 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆274Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,082Updated last month
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 6 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆331Updated 2 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆487Updated last month
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆842Updated last month
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,604Updated 3 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆667Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆629Updated this week
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆715Updated 3 months ago
• splinedrive / kianRiscV
  RISC-V Linux SoC, marchID: 0x2b
  ☆898Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆288Updated 2 weeks ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆289Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆342Updated this week
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 2 months ago