algorhtym / riscv-resourcesLinks
An organized and comprehensive library of resources for the RISC-V community and anyone interested in getting involved with the RISC-V ecosystem, relevantly categorized based on topics and knowledge/experience level, built by the RISC-V community.
☆19Updated last year
Alternatives and similar repositories for riscv-resources
Users that are interested in riscv-resources are comparing it to the libraries listed below
Sorting:
- this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by …☆26Updated 3 weeks ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆139Updated 3 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆187Updated last week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆207Updated 2 months ago
- SystemVerilog Tutorial☆166Updated 3 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆120Updated 4 years ago
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆25Updated 2 years ago
- Self checking RISC-V directed tests☆112Updated 3 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆112Updated last week
- A Single Cycle Risc-V 32 bit CPU☆49Updated last week
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆113Updated 3 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆211Updated 3 weeks ago
- Verilog/SystemVerilog Guide☆72Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆133Updated 5 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆385Updated last month
- Curriculum for a university course to teach chip design using open source EDA tools☆107Updated last year
- ☆66Updated 2 years ago
- RISC-V microcontroller IP core developed in Verilog☆178Updated 4 months ago
- RISC-V SystemC-TLM simulator☆319Updated 8 months ago
- Modeling Architectural Platform☆202Updated last week
- 2D Systolic Array Multiplier☆18Updated last year
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆265Updated 3 months ago
- This repository contains the design files of RISC-V Pipeline Core☆51Updated 2 years ago
- ☆143Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- Collect some IC textbooks for learning.☆161Updated 3 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆382Updated last month
- Chisel examples and code snippets☆257Updated 3 years ago
- lowRISC Style Guides☆450Updated 2 months ago