Alternatives and similar repositories for Ripes

Users that are interested in Ripes are comparing it to the libraries listed below

• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,685Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,756Updated 2 weeks ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,299Updated last week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,465Updated 10 months ago
• cvut / qtrvsim
  RISC-V CPU simulator for education purposes
  ☆550Updated last week
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,437Updated 3 weeks ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,882Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,395Updated 3 months ago
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆988Updated 5 months ago
• vortexgpgpu / vortex
  ☆1,499Updated this week
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,227Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,455Updated last week
• BrunoLevy / learn-fpga
  Learning FPGA, yosys, nextpnr, and RISC-V
  ☆2,785Updated 2 months ago
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,075Updated 2 months ago
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,868Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,042Updated this week
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,359Updated last month
• riscv-collab / riscv-gnu-toolchain
  GNU toolchain for RISC-V, including GCC
  ☆3,900Updated this week
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,164Updated 2 years ago
• riscv-software-src / riscv-tests
  ☆997Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,011Updated 3 years ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆757Updated this week
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆945Updated 2 weeks ago
• riscv-non-isa / riscv-asm-manual
  RISC-V Assembly Programmer's Manual
  ☆1,503Updated 3 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,576Updated this week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,755Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,781Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,836Updated this week
• riscv / riscv-isa-manual
  RISC-V Instruction Set Manual
  ☆4,054Updated this week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆832Updated this week