RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
☆351Apr 2, 2026Updated last month
Alternatives and similar repositories for awesome-riscv
Users that are interested in awesome-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Curated list of awesome resources related with RISC-V☆97Aug 17, 2022Updated 3 years ago
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆1,589Apr 15, 2026Updated last month
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆22Jul 21, 2025Updated 10 months ago
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆11Sep 19, 2025Updated 8 months ago
- ☆13Feb 1, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆15Nov 30, 2023Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,248Sep 18, 2021Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,939May 13, 2026Updated last week
- 😎 A curated list of awesome RISC-V implementations☆143Mar 12, 2023Updated 3 years ago
- My 32-bit RISC CPU for smallish FPGAs☆19Apr 20, 2022Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆57Jul 9, 2021Updated 4 years ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆17Sep 15, 2020Updated 5 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12May 3, 2026Updated 2 weeks ago
- ☆22Sep 26, 2025Updated 7 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,231Apr 17, 2026Updated last month
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,149Jun 27, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,262Updated this week
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆129May 8, 2026Updated 2 weeks ago
- CORE-V Family of RISC-V Cores☆352Mar 31, 2026Updated last month
- List of awesome open source hardware tools, generators, and reusable designs☆2,335Mar 2, 2026Updated 2 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆80May 12, 2026Updated last week
- Rocket Chip Generator☆3,773Apr 21, 2026Updated last month
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,161Mar 11, 2026Updated 2 months ago
- A curated list of awesome open source hardware design tools☆88Jun 20, 2025Updated 11 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,875May 7, 2026Updated 2 weeks ago
- KVM RISC-V HowTOs☆48Jun 9, 2022Updated 3 years ago
- Random instruction generator for RISC-V processor verification☆1,298Apr 3, 2026Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆334May 15, 2026Updated last week
- Berkeley's Spatial Array Generator☆1,317Mar 29, 2026Updated last month
- RISC-V CPU Core☆428Jun 24, 2025Updated 10 months ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- The Ultra-Low Power RISC-V Core☆1,833Aug 6, 2025Updated 9 months ago
- ☆17Feb 16, 2023Updated 3 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆348Dec 2, 2025Updated 5 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,142Feb 11, 2026Updated 3 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆683Apr 16, 2026Updated last month
- A curated list of awesome WAGO tutorials, guides, projects and resources.☆14Apr 3, 2021Updated 5 years ago