RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
☆365Apr 2, 2026Updated 3 months ago
Alternatives and similar repositories for awesome-riscv
Users that are interested in awesome-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Curated list of awesome resources related with RISC-V☆99Aug 17, 2022Updated 3 years ago
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆1,654Jun 8, 2026Updated 3 weeks ago
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆24Jul 21, 2025Updated 11 months ago
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆10Sep 19, 2025Updated 9 months ago
- ☆13Feb 1, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 32-bit Superscalar RISC-V CPU☆1,266Sep 18, 2021Updated 4 years ago
- ☆15Nov 30, 2023Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,983Updated this week
- 😎 A curated list of awesome RISC-V implementations☆144Mar 12, 2023Updated 3 years ago
- My 32-bit RISC CPU for smallish FPGAs☆19Apr 20, 2022Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆60Jul 9, 2021Updated 4 years ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆18Sep 15, 2020Updated 5 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Jun 9, 2026Updated 3 weeks ago
- ☆22Sep 26, 2025Updated 9 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FPGA based microcomputer sandbox for software and RTL experimentation☆81Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,255May 29, 2026Updated last month
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,233Jun 27, 2024Updated 2 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,299Jun 22, 2026Updated last week
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆132May 8, 2026Updated last month
- CORE-V Family of RISC-V Cores☆358Mar 31, 2026Updated 3 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆358Dec 2, 2025Updated 7 months ago
- List of awesome open source hardware tools, generators, and reusable designs☆2,358Mar 2, 2026Updated 4 months ago
- Rocket Chip Generator☆3,803Jun 2, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,186Jun 26, 2026Updated last week
- A curated list of awesome open source hardware design tools☆88Jun 20, 2025Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,933Jun 11, 2026Updated 3 weeks ago
- KVM RISC-V HowTOs☆49Jun 9, 2022Updated 4 years ago
- ☆12Oct 1, 2021Updated 4 years ago
- Random instruction generator for RISC-V processor verification☆1,316Apr 3, 2026Updated 2 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆346Jun 25, 2026Updated last week
- Berkeley's Spatial Array Generator☆1,365Jun 24, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V CPU Core☆439Jun 24, 2025Updated last year
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆12May 2, 2022Updated 4 years ago
- The Ultra-Low Power RISC-V Core☆1,867Aug 6, 2025Updated 10 months ago
- ☆17Feb 16, 2023Updated 3 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,177Feb 11, 2026Updated 4 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆689Jun 22, 2026Updated last week