RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
☆375Apr 2, 2026Updated 3 months ago
Alternatives and similar repositories for awesome-riscv
Users that are interested in awesome-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆1,690Updated this week
- Curated list of awesome resources related with RISC-V☆100Aug 17, 2022Updated 3 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆582Updated this week
- CORE-V Family of RISC-V Cores☆364Mar 31, 2026Updated 3 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,028Updated this week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- 32-bit Superscalar RISC-V CPU☆1,282Sep 18, 2021Updated 4 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,201Updated this week
- FPGA based microcomputer sandbox for software and RTL experimentation☆82Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,274Jun 27, 2024Updated 2 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆355Updated this week
- A Linux-capable RISC-V multicore for and by the world☆822Jul 13, 2026Updated last week
- Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.☆23Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,339Updated this week
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆60Jul 9, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,267May 29, 2026Updated last month
- CVA6 softcore contest☆23Jul 8, 2026Updated 2 weeks ago
- Rocket Chip Generator☆3,822Jun 2, 2026Updated last month
- 😎 A curated list of awesome RISC-V implementations☆144Mar 12, 2023Updated 3 years ago
- ☆13Feb 1, 2025Updated last year
- RISC-V CPU Core☆442Jun 24, 2025Updated last year
- 3-stage RV32IMACZb* processor with debug☆1,077Updated this week
- This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory,…☆17Sep 5, 2024Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆237Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- RISC-V Verification Interface☆157Jun 11, 2026Updated last month
- A fully open source low cost FPGA board for makers , hobbyist and student for endless possibility.☆43Dec 13, 2025Updated 7 months ago
- Berkeley's Spatial Array Generator☆1,404Jun 30, 2026Updated 3 weeks ago
- ☆15Nov 30, 2023Updated 2 years ago
- List of awesome open source hardware tools, generators, and reusable designs☆2,373Mar 2, 2026Updated 4 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆175Feb 2, 2026Updated 5 months ago
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆26Jul 21, 2025Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,980Jul 14, 2026Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,198Feb 11, 2026Updated 5 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Advanced Architecture Labs with CVA6☆81Jan 16, 2024Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆224Jul 14, 2026Updated last week
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆99Apr 25, 2026Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆121Jun 18, 2026Updated last month
- RISC-V Integrated Matrix Development Repository☆25Updated this week
- RISC-V microcontroller for embedded, FPGA and ASIC applications☆200Updated this week
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆18Sep 15, 2020Updated 5 years ago