0BAB1 / HOLY_CORE_COURSELinks
Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.
☆198Updated last week
Alternatives and similar repositories for HOLY_CORE_COURSE
Users that are interested in HOLY_CORE_COURSE are comparing it to the libraries listed below
Sorting:
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆402Updated this week
- ☆401Updated 5 months ago
- 3-stage RV32IMACZb* processor with debug☆910Updated last week
- [BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.☆57Updated last month
- A simple RISC V core for teaching☆193Updated 3 years ago
- It contains a curated list of awesome RISC-V Resources.☆243Updated 6 months ago
- RISC-V Linux SoC, marchID: 0x2b☆933Updated last week
- ☆337Updated 2 years ago
- CORE-V Family of RISC-V Cores☆285Updated 5 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆306Updated 5 months ago
- RISC-V microcontroller IP core developed in Verilog☆176Updated 3 months ago
- FOSS Flow For FPGA☆400Updated 7 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆115Updated 4 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆141Updated 4 years ago
- HomebrewGPU is a simple ray tracing GPU on FPGA which implements basic ray-primitive intersection, BVH traversal, shadowing, reflection a…☆207Updated 2 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆272Updated this week
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆77Updated 2 months ago
- Linux capable RISC-V SoC designed to be readable and useful.☆151Updated 2 months ago
- An rv32i inspired ISA, SIMT GPU implementation in system-verilog.☆197Updated 5 months ago
- A tiny system built on a small QMTECH board☆107Updated 4 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆263Updated 2 months ago
- A Linux-capable RISC-V multicore for and by the world☆720Updated 3 months ago
- A simple superscalar out-of-order RISC-V microprocessor☆212Updated 5 months ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆668Updated 2 weeks ago
- An overview of TL-Verilog resources and projects☆80Updated 4 months ago
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆980Updated last week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- Opensource DDR3 Controller☆371Updated last month
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆155Updated last year
- Waveform Viewer Extension for VScode☆220Updated this week