0BAB1 / HOLY_CORE_COURSE
Learn how to build our own RV32I core and use it on FPGA.
☆92Updated last month
Alternatives and similar repositories for HOLY_CORE_COURSE:
Users that are interested in HOLY_CORE_COURSE are comparing it to the libraries listed below
- A tiny system built on a small QMTECH board☆102Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆310Updated this week
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆121Updated 3 years ago
- A simple RISC V core for teaching☆176Updated 3 years ago
- CORE-V Family of RISC-V Cores☆231Updated last week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆267Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆224Updated this week
- Linux capable RISC-V SoC designed to be readable and useful.☆138Updated 4 months ago
- Opensource DDR3 Controller☆265Updated this week
- Example LED blinking project for your FPGA dev board of choice☆170Updated 2 months ago
- Experimental flows using nextpnr for Xilinx devices☆225Updated 4 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆147Updated 8 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- RISC-V 32-bit microcontroller developed in Verilog☆167Updated 4 months ago
- HomebrewGPU is a simple ray tracing GPU on FPGA which implements basic ray-primitive intersection, BVH traversal, shadowing, reflection a…☆197Updated last year
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆126Updated 2 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆414Updated 5 months ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆88Updated 4 years ago
- ☆309Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆71Updated last year
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆208Updated 10 months ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆240Updated last month
- It contains a curated list of awesome RISC-V Resources.☆190Updated last month
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆62Updated 5 months ago
- FOSS Flow For FPGA☆369Updated last month
- Communication framework for RTL simulation and emulation.☆272Updated last week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆312Updated last week
- Doom classic port to lightweight RISC‑V☆87Updated 2 years ago
- A simple superscalar out-of-order RISC-V microprocessor☆192Updated this week