Alternatives and similar repositories for HOLY_CORE_COURSE

Users that are interested in HOLY_CORE_COURSE are comparing it to the libraries listed below

• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆455Updated last week
• 0BAB1 / BRH_Tutorials
  [BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.
  ☆67Updated 5 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆198Updated 4 years ago
• spzbrnmrc / Tiny-Vedas
  A highly-configurable RISC-V Core
  ☆28Updated this week
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆284Updated 11 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆368Updated 2 years ago
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆436Updated 9 months ago
• chipfoundry / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆325Updated last month
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆165Updated 4 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆312Updated 10 months ago
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆95Updated 6 months ago
• librelane / librelane
  ASIC implementation flow infrastructure, successor to OpenLane
  ☆227Updated 2 weeks ago
• Wren6991 / Hazard3
  3-stage RV32IMACZb* processor with debug
  ☆971Updated 2 weeks ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆150Updated 5 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆284Updated 7 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆312Updated last week
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆178Updated this week
• fallingcat / HomebrewGPU
  HomebrewGPU is a simple ray tracing GPU built on FPGA, featuring basic ray–primitive intersection, BVH traversal, shadowing, reflection, …
  ☆216Updated 2 years ago
• StefanSchippers / xschem
  A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…
  ☆427Updated 2 weeks ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆130Updated 3 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆402Updated this week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆224Updated 10 months ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆693Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated 11 months ago
• Grubre / smol-gpu
  An rv32i inspired ISA, SIMT GPU implementation in system-verilog.
  ☆213Updated 10 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated last week
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆300Updated last week
• splinedrive / kianRiscV
  RISC-V XV6/Linux SoC, marchID: 0x2b
  ☆1,014Updated last week