Alternatives and similar repositories for HOLY_CORE_COURSE

Users that are interested in HOLY_CORE_COURSE are comparing it to the libraries listed below

• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆415Updated last week
• 0BAB1 / BRH_Tutorials
  [BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.
  ☆64Updated 3 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆259Updated 8 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆300Updated 7 months ago
• Wren6991 / Hazard3
  3-stage RV32IMACZb* processor with debug
  ☆934Updated last week
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆422Updated 7 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆350Updated 2 years ago
• splinedrive / kianRiscV
  RISC-V XV6/Linux SoC, marchID: 0x2b
  ☆969Updated last week
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆129Updated 4 years ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆313Updated 7 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆387Updated 3 months ago
• siliscale / Tiny-Vedas
  A highly-configurable RISC-V Core
  ☆25Updated last month
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆678Updated this week
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆149Updated 4 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆738Updated 2 weeks ago
• fallingcat / HomebrewGPU
  HomebrewGPU is a simple ray tracing GPU on FPGA which implements basic ray-primitive intersection, BVH traversal, shadowing, reflection a…
  ☆212Updated 2 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆407Updated 9 months ago
• iic-jku / IIC-OSIC-TOOLS
  IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…
  ☆669Updated this week
• ecilasun / tinysys
  A tiny system built on a small QMTECH board
  ☆109Updated 6 months ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆183Updated 5 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆287Updated this week
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆272Updated 4 months ago
• getinstachip / vpm
  Verilog package manager written in Rust
  ☆143Updated last year
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆317Updated 5 months ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,190Updated this week
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆88Updated 4 months ago
• aritramanna / 3-Wide-RISC-V-OOO-RV32-IM-Processor
  3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism
  ☆17Updated last month
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆270Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆668Updated 3 months ago