Alternatives and similar repositories for HaDes-V:

Users that are interested in HaDes-V are comparing it to the libraries listed below

• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆62Updated last week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆84Updated last year
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆46Updated this week
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆77Updated last week
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 3 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆61Updated this week
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆38Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆111Updated last year
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 5 months ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 7 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆65Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆38Updated last year
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated last week
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆55Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆66Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆37Updated 10 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated 3 months ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 2 months ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆29Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆80Updated last week
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆44Updated last year
• chipsalliance / uvm-verilator
  ☆88Updated last year
• kerimturak / tcore-rv32imc
  ☆12Updated last month
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆24Updated 3 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆81Updated 2 weeks ago