Alternatives and similar repositories for HaDes-V

Users that are interested in HaDes-V are comparing it to the libraries listed below

• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆115Updated 3 weeks ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆108Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆137Updated last month
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆58Updated 3 months ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆109Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆69Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆120Updated 2 months ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆63Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆161Updated this week
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆65Updated 3 years ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 8 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated this week
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆76Updated 3 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 6 months ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆172Updated 4 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆197Updated last week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆156Updated 2 months ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆96Updated 2 months ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆48Updated 2 months ago
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆108Updated 2 weeks ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated 3 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆47Updated last week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆39Updated 2 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated 2 months ago