abdelazeem201 / ASIC-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
☆296Updated 5 months ago
Alternatives and similar repositories for ASIC-Design-Roadmap:
Users that are interested in ASIC-Design-Roadmap are comparing it to the libraries listed below
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆224Updated 6 months ago
- This repo provide an index of VLSI content creators and their materials☆141Updated 5 months ago
- 100 Days of RTL☆348Updated 6 months ago
- ☆310Updated last year
- Awesome ASIC design verification☆280Updated 3 years ago
- A roadmap for those who want to build a career as an FPGA / ASIC Engineer☆288Updated 2 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆105Updated last year
- lowRISC Style Guides☆388Updated 5 months ago
- Instructions & Assignments for COD Lab - UE22EC352A☆4Updated 2 months ago
- ☆61Updated 2 weeks ago
- ☆108Updated last year
- SystemVerilog Tutorial☆123Updated this week
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆511Updated last year
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆146Updated 2 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆64Updated last year
- ECE 3300 HDL Code☆43Updated 2 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆13Updated last year
- Verilog HDL files☆121Updated 8 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆140Updated 7 months ago
- The UVM written in Python☆400Updated last month
- training labs and examples☆411Updated 2 years ago
- ☆130Updated 2 years ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆415Updated this week
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆24Updated 9 months ago
- Common SystemVerilog components☆570Updated last week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆507Updated 3 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆308Updated 2 weeks ago
- This repository contains the design files of RISC-V Single Cycle Core☆32Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆297Updated 9 months ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆617Updated 3 months ago