abdelazeem201 / ASIC-Design-RoadmapLinks
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
☆446Updated 6 months ago
Alternatives and similar repositories for ASIC-Design-Roadmap
Users that are interested in ASIC-Design-Roadmap are comparing it to the libraries listed below
Sorting:
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆289Updated 7 months ago
- 100 Days of RTL☆405Updated last year
- This repo provide an index of VLSI content creators and their materials☆162Updated last year
- ECE 3300 HDL Code☆62Updated 2 years ago
- ☆115Updated 2 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆170Updated last year
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆30Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆52Updated last year
- SystemVerilog Tutorial☆188Updated last month
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆21Updated 4 years ago
- ☆91Updated last month
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆124Updated 3 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated 2 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆106Updated 2 years ago
- A roadmap for those who want to build a career as an FPGA / ASIC Engineer☆488Updated last year
- opensource EDA tool flor VLSI design☆36Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆130Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆99Updated last year
- Verilog HDL files☆165Updated last year
- Verilog implementation of multi-stage 32-bit RISC-V processor☆153Updated 5 years ago
- ☆13Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆151Updated 3 months ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆20Updated last year
- lowRISC Style Guides☆474Updated 2 months ago
- ☆17Updated 2 years ago
- ☆372Updated 2 years ago
- Implementation of RISC-V RV32I☆27Updated 3 years ago