Nuclei-Software / NMSIS

Related projects: ⓘ

• Nuclei-Software / nuclei-sdk
  Nuclei RISC-V Software Development Kit
  ☆118Updated this week
• ilg-archived / riscv-none-gcc
  The GNU MCU Eclipse RISC-V Embedded GCC
  ☆76Updated 4 years ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆128Updated 2 months ago
• XUANTIE-RV / csi-nn2
  An optimized neural network operator library for chips base on Xuantie CPU.
  ☆83Updated 2 months ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆129Updated 2 months ago
• Nuclei-Software / nuclei-board-labs
  Nuclei Board Labs
  ☆52Updated 8 months ago
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 4 years ago
• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆87Updated 2 months ago
• chipsalliance / riscv-fw-infrastructure
  SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...
  ☆24Updated 2 years ago
• nucleisys / n200-doc
  Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php
  ☆25Updated 3 years ago
• xpack-dev-tools / riscv-none-embed-gcc-xpack
  DEPRECATED: Please update to risc-none-elf-gcc-xpack
  ☆114Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆61Updated 2 months ago
• c-sky / xuantie-vector-demos
  ☆10Updated 4 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆66Updated 3 years ago
• bigmagic123 / d1-nezha-baremeta
  riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)
  ☆76Updated 2 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆72Updated 8 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆93Updated 2 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆119Updated 5 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆28Updated 4 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆20Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 2 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆51Updated last year
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆73Updated 5 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆44Updated 4 years ago
• PulseRain / Reindeer_Step
  Reindeer Soft CPU for Step CYC10 FPGA board
  ☆25Updated 3 years ago
• eembc / audiomark
  Developer repository for the AudioMark(tm) benchmark.
  ☆15Updated 3 months ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆140Updated 9 months ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆53Updated last month
• open-isa-rv32m1 / rv32m1_sdk_riscv
  SDK for RV32M1 RISCV cores
  ☆17Updated 5 years ago
• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago