xiaoerlang0359 / E203plus
upgrade to e203 (a risc-v core)
☆37Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for E203plus
- AXI总线连接器☆91Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆31Updated 3 months ago
- AXI协议规范中文翻译版☆132Updated 2 years ago
- Step by step tutorial for building CortexM0 SoC☆35Updated 2 years ago
- ☆52Updated 8 years ago
- ☆63Updated 2 years ago
- Cortex M0 based SoC☆70Updated 3 years ago
- ☆36Updated 2 years ago
- ☆9Updated 4 years ago
- commit rtl and build cosim env☆35Updated 7 months ago
- ☆34Updated 9 years ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆52Updated 8 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated last week
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- CPU Design Based on RISCV ISA☆76Updated 5 months ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- ARM中通过APB总线连接的UART模块☆59Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆67Updated 3 years ago
- AXI Interconnect☆46Updated 3 years ago
- ☆26Updated 5 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆18Updated 7 months ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。☆43Updated 11 months ago
- ☆62Updated 3 months ago
- IC Verification & SV Demo☆45Updated 3 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆11Updated 6 months ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆68Updated 6 years ago