xiaoerlang0359 / E203plusLinks
upgrade to e203 (a risc-v core)
☆45Updated 5 years ago
Alternatives and similar repositories for E203plus
Users that are interested in E203plus are comparing it to the libraries listed below
Sorting:
- AXI总线连接器☆105Updated 5 years ago
- ☆74Updated 10 years ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- ☆11Updated 5 years ago
- AXI DMA 32 / 64 bits☆124Updated 11 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- Open IP in Hardware Description Language.☆29Updated 2 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆65Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- ☆38Updated 10 years ago
- CPU Design Based on RISCV ISA☆129Updated last year
- Cortex M0 based SoC☆76Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- IC Verification & SV Demo☆57Updated 4 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆28Updated 3 years ago
- ☆47Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆60Updated 9 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- round robin arbiter☆77Updated 11 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆154Updated 8 months ago
- ahb scram controller, design and verification☆28Updated 7 years ago
- AXI Interconnect☆56Updated 4 years ago
- AHB DMA 32 / 64 bits☆59Updated 11 years ago
- Step by step tutorial for building CortexM0 SoC☆39Updated 3 years ago
- HYF's high quality verilog codes☆16Updated last year