Qingchuan-Ma / IC-designerLinks
note about IC knowledge
☆10Updated 2 years ago
Alternatives and similar repositories for IC-designer
Users that are interested in IC-designer are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆130Updated 3 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- ☆115Updated 5 years ago
- ☆43Updated 4 years ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆97Updated last month
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆42Updated 2 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆191Updated 7 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆39Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆222Updated 2 years ago
- IC implementation of Systolic Array for TPU☆272Updated 10 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆23Updated last year
- Hardware accelerator for convolutional neural networks☆52Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 7 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆186Updated last year
- IC implementation of TPU☆129Updated 5 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- ☆34Updated 6 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆20Updated last year
- ☆10Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆119Updated 12 years ago