Qingchuan-Ma / IC-designerView external linksLinks
note about IC knowledge
☆10Sep 7, 2022Updated 3 years ago
Alternatives and similar repositories for IC-designer
Users that are interested in IC-designer are comparing it to the libraries listed below
Sorting:
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated 5 months ago
- ☆72Apr 23, 2023Updated 2 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆24Jul 17, 2025Updated 6 months ago
- Network on chip based neural network accelerator☆10Mar 25, 2021Updated 4 years ago
- An Address Event Representation toolbox for loading and visualising event data files in Python☆11Jul 6, 2023Updated 2 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆12Aug 9, 2019Updated 6 years ago
- FlappyBird愤怒的小鸟 c++游戏实现 学习代码☆10Nov 16, 2018Updated 7 years ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆13May 22, 2025Updated 8 months ago
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 10 months ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Feb 9, 2026Updated last week
- Tencent IOT SDK for rt-thread Package 是基于腾讯云物联网开发平台（IoT Explorer）设备端 SDK在RThread环境开发的软件包，配合平台对设备数据模板化的定义，实现和云端基于数据模板协议的数据交互框架，开发者基于IoT_Ex…☆10Jul 8, 2025Updated 7 months ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Nov 12, 2025Updated 3 months ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆13Jan 28, 2019Updated 7 years ago
- realtime-emd(Empirical Mode Decomposition) from code.google.com/archive/p/realtime-emd/☆14Aug 9, 2016Updated 9 years ago
- The source code for the paper entitled "A Tandem Learning Rule for Effective Training and Rapid Inference of Deep Spiking Neural Networks…☆14Jul 4, 2021Updated 4 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 2 years ago
- Toolchain of PAICORE.☆15Feb 5, 2026Updated last week
- ☆14Feb 24, 2025Updated 11 months ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 5 years ago
- Find Tan Kuku plugin for nonebot2☆11Nov 3, 2025Updated 3 months ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Dec 18, 2025Updated last month
- ☆10Oct 8, 2021Updated 4 years ago
- ☆15Mar 24, 2023Updated 2 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Performance and diagnostic tools for Arm CMN on-chip interconnects☆22Jan 28, 2026Updated 2 weeks ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- A Self driving car agent developed using Reinforcement learning Actor Critic Algorithm on TORCS Simulator.☆12Aug 31, 2021Updated 4 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Pr…☆10Oct 12, 2022Updated 3 years ago
- 重庆大学计算机学院2018级计算机体系结构cache设计☆11Jan 4, 2021Updated 5 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Little RISC-V 3-stage Pipeline CPU☆16Jun 14, 2021Updated 4 years ago