Qingchuan-Ma / IC-designer
note about IC knowledge
☆9Updated 2 years ago
Alternatives and similar repositories for IC-designer:
Users that are interested in IC-designer are comparing it to the libraries listed below
- verilog实现TPU中的脉动阵列计算卷积的module☆91Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆55Updated last month
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- ☆104Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- ☆31Updated 5 years ago
- 关于移植模型至gemmini的文档☆23Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- 一个基于AXI接口的PL端卷积加速器,可由PS端调用☆11Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆94Updated 4 years ago
- ☆80Updated last month
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆17Updated 11 months ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Updated 6 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆12Updated 8 months ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆38Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated 3 weeks ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆18Updated 2 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 3 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- ☆19Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆29Updated 2 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆55Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago