har-in-air / SIPEED_TANG_PRIMER

Related projects ⓘ

Alternatives and complementary repositories for SIPEED_TANG_PRIMER

• tinyvision-ai-inc / Vision-FPGA-SoM
  tinyVision.ai Vision & Sensor FPGA System on Module
  ☆43Updated 3 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 3 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆24Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆36Updated 5 months ago
• gtjennings1 / UPDuino-OV7670-Camera
  Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module
  ☆21Updated 6 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆20Updated 9 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆40Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆17Updated 5 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆25Updated 3 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆36Updated 8 months ago
• rbarzic / arty-cm0-designstart
  A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
  ☆12Updated 6 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated 10 months ago
• micro-FPGA / riscv-contest-2018
  RISCV SoftCPU Contest 2018
  ☆14Updated 5 years ago
• Digilent / Arty-A7-35-XADC
  ☆18Updated 4 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 5 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆43Updated last year
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 2 years ago
• kazkojima / colorlight-i5-tips
  Tiny tips for Colorlight i5 FPGA board
  ☆55Updated 3 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆19Updated 4 years ago
• olofk / observer
  ☆40Updated 4 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆74Updated 4 years ago
• FPGA-Research-Manchester / byteman
  Bitstream relocation and manipulation tool.
  ☆39Updated last year