har-in-air / SIPEED_TANG_PRIMER
Projects using the Sipeed Tang Primer FPGA development board
☆13Updated 4 years ago
Alternatives and similar repositories for SIPEED_TANG_PRIMER:
Users that are interested in SIPEED_TANG_PRIMER are comparing it to the libraries listed below
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- Wishbone interconnect utilities☆38Updated 7 months ago
- USB Full Speed PHY☆39Updated 4 years ago
- tinyVision.ai Vision & Sensor FPGA System on Module☆46Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆24Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 8 months ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆22Updated 3 years ago
- Future Electronics Creative Eval Board featuring a Microsemi SmartFusion2 or IGLOO2 FPGA☆16Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆59Updated 6 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆21Updated 3 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- ☆17Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆83Updated 6 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- MMC (and derivative standards) host controller☆22Updated 4 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆41Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- Tiny tips for Colorlight i5 FPGA board☆56Updated 3 years ago
- turbo 8051☆28Updated 7 years ago
- IceCore Ice40 HX based modular core☆46Updated 3 years ago
- A 5$ Xilinx ZYNQ development board.☆25Updated last year
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 6 years ago
- Master-thesis-final☆18Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated last month
- Digital FM Radio Receiver for FPGA☆60Updated 9 years ago
- FPGA USB 1.1 Low-Speed Implementation☆33Updated 6 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆20Updated 11 months ago