har-in-air / SIPEED_TANG_PRIMER

Related projects ⓘ

Alternatives and complementary repositories for SIPEED_TANG_PRIMER

• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 3 years ago
• tinyvision-ai-inc / Vision-FPGA-SoM
  tinyVision.ai Vision & Sensor FPGA System on Module
  ☆44Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 5 months ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆24Updated 4 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆15Updated 4 months ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆23Updated 4 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated 11 months ago
• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆12Updated 9 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆19Updated 4 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• openXC7 / xc7k325t-blinky-nextpnr
  ☆43Updated last year
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆19Updated last month
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆30Updated last year
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆40Updated last year
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆82Updated 6 years ago
• Juninho99 / FPGA_TangNano20k_Hand_Coded_DIP_LCD_Camera
  Master-thesis-final
  ☆18Updated last year
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆21Updated 9 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 2 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆26Updated last month
• emb4fun / neorv32-examples
  Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.
  ☆15Updated this week
• rbarzic / arty-cm0-designstart
  A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
  ☆12Updated 6 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆29Updated 4 years ago
• merledu / symbiflow-magic
  This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
  ☆10Updated 3 years ago
• AngeloJacobo / ULX3S_FPGA_Sobel_Edge_Detection_OV7670
  Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
  ☆15Updated 3 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆22Updated 4 years ago
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆26Updated 6 years ago
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆14Updated 8 months ago