Alternatives and similar repositories for pyocdriscv32

Users that are interested in pyocdriscv32 are comparing it to the libraries listed below

• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆31Updated 4 years ago
• Wren6991 / HyperRam
  simple hyperram controller
  ☆12Updated 7 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• jeras / fpga-hdl
  A set of small Verilog projects, to simulate and implement on FPGA development boards
  ☆15Updated 7 years ago
• tomverbeure / usb_system
  SpinalHDL USB system for the ULPI based Arrow DECA board
  ☆20Updated 4 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 7 years ago
• kazkojima / lunauac2-pdm
  A LiteX module implementing a USB UAC2 module with simple PDM in/out
  ☆16Updated 3 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆66Updated 2 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆33Updated 5 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆35Updated 2 years ago
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• StereoNinja / StereoNinjaFPGA
  Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board
  ☆32Updated 2 years ago
• tomverbeure / jtag_uart_example
  Mini CPU design with JTAG UART support
  ☆21Updated 4 years ago
• lawrie / blackicemxbook
  ☆27Updated 6 years ago
• OldRepoPreservation / mpeg2fpga
  An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.
  ☆26Updated 6 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• nockieboy / gpu
  Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
  ☆18Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆34Updated 5 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆49Updated last month
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆20Updated last year
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆97Updated 5 years ago
• davidcastells / py4hw
  Hardware Design/Visualization/Simulation/RTLGeneration Framework
  ☆16Updated last week
• tomverbeure / fpga_quick_ram_update
  Quickly update a bitstream with new RAM contents
  ☆16Updated 4 years ago
• har-in-air / SIPEED_TANG_PRIMER
  Projects using the Sipeed Tang Primer FPGA development board
  ☆16Updated 5 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆33Updated 4 years ago
• lambdaconcept / lambdasoc
  ☆44Updated 11 months ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• lambdaconcept / amaranth-to-litex
  Use amaranth-to-litex to simply import Amaranth code into a Litex project.
  ☆15Updated last year
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆20Updated last year