Nuclei E203 with yolo accelerator based on xc7k325
☆19Jul 19, 2024Updated last year
Alternatives and similar repositories for yolo_e203_fpga
Users that are interested in yolo_e203_fpga are comparing it to the libraries listed below
Sorting:
- ☆11Aug 2, 2023Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆23May 7, 2024Updated last year
- ☆56Apr 19, 2023Updated 2 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆271Apr 1, 2024Updated last year
- Tutorials on Vitis AI Created by LogicTronix!☆34Jul 5, 2024Updated last year
- ☆32Mar 31, 2025Updated 11 months ago
- Zynq/FPGA实现CNN手写数字(0-9)识别☆38Dec 14, 2024Updated last year
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆13Aug 1, 2023Updated 2 years ago
- 2048 Game created via Verilog, loaded on an FPGA board and VGA monitor.☆13Mar 25, 2022Updated 3 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆16Mar 12, 2023Updated 2 years ago
- LeNet-5 use c achieve☆13Jan 10, 2020Updated 6 years ago
- kernel port for juicevm☆13May 25, 2021Updated 4 years ago
- ☆10Nov 22, 2022Updated 3 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- some interesting demos for starters☆94Dec 2, 2022Updated 3 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- ☆17Apr 7, 2022Updated 3 years ago
- Sample scripts for FPGA-based AI Edge Contest 2019☆11Mar 20, 2020Updated 5 years ago
- Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision☆12Jan 19, 2026Updated last month
- Official Repo for "Multi-objective Differentiable Neural Architecture Search"☆15Jul 12, 2024Updated last year
- verilog实现systolic array及配套IO☆12Dec 2, 2024Updated last year
- FPGA创新设计大赛全国二等奖,Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Aug 16, 2024Updated last year
- upgrade to e203 (a risc-v core)☆45Aug 9, 2020Updated 5 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Dec 12, 2023Updated 2 years ago
- ☆13Jul 10, 2024Updated last year
- ☆17Oct 15, 2023Updated 2 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆143Jul 20, 2023Updated 2 years ago
- Implement Tiny YOLO v3 on ZYNQ☆312Apr 14, 2025Updated 10 months ago
- ☆11Oct 10, 2019Updated 6 years ago
- A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.☆12Jul 29, 2021Updated 4 years ago
- SCU Firmware (based on Chromium EC) for embedded USRP Devices. Report issues on the UHD repository!☆15Sep 4, 2024Updated last year
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆20Nov 26, 2018Updated 7 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Jun 4, 2024Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆17Dec 23, 2025Updated 2 months ago