Zero0Hero / yolo_e203_fpga
Nuclei E203 with yolo accelerator based on xc7k325
☆10Updated 7 months ago
Alternatives and similar repositories for yolo_e203_fpga:
Users that are interested in yolo_e203_fpga are comparing it to the libraries listed below
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆35Updated 5 years ago
- some interesting demos for starters☆68Updated 2 years ago
- ☆14Updated last year
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆80Updated last year
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆34Updated 7 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆46Updated last week
- ☆101Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- ☆14Updated last year
- An LeNet RTL implement onto FPGA☆41Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆141Updated 5 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆136Updated last year
- ☆60Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆81Updated 3 years ago
- ☆51Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆138Updated 4 months ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆28Updated 3 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated last year
- CNN accelerator implemented with Spinal HDL☆145Updated last year
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆28Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆59Updated 6 months ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆51Updated 10 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆57Updated this week
- Spiking Neural Network RTL Implementation☆52Updated 3 years ago
- ☆16Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆150Updated 11 months ago
- C++ code for HLS FPGA implementation of transformer☆16Updated 5 months ago