Alternatives and similar repositories for AXI4-Stream-FIR-filter

Users that are interested in AXI4-Stream-FIR-filter are comparing it to the libraries listed below

• DeamonYang / FPGA_SYNC_ASYNC_FIFO
  FPGA 同步FIFO与异步FIFO
  ☆31Updated 6 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆29Updated 5 years ago
• cterrill26 / FPGA_AudioVisualizer
  Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…
  ☆16Updated 5 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆37Updated 10 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆47Updated 9 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆61Updated 3 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆68Updated 5 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆72Updated 3 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆53Updated last month
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆44Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆22Updated 6 years ago
• Frogwells / fpga_cmos_design
  这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西
  ☆36Updated 7 years ago
• lauchinyuan / FPGA_DDR3_Ctrl
  An AXI DDR3 SDRAM controller for FPGA
  ☆41Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆75Updated 3 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆59Updated 9 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆75Updated last year
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• shun6-6 / Tri_Eth_UDP_pro_stack
  基于FPGA的三速以太网UDP协议栈设计
  ☆30Updated last year
• cjhonlyone / NandFlashController
  AXI Interface Nand Flash Controller (Sync mode)
  ☆96Updated last year
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 5 years ago
• chenshuo / veriloglabs
  Undergraduate digital circuit laboratory
  ☆28Updated last year
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆30Updated 4 years ago
• JefferyLi0903 / MMC
  MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计
  ☆22Updated 2 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆52Updated 11 years ago