chengyih001 / ResNet18_fpga_acceleratorLinks
☆11Updated last year
Alternatives and similar repositories for ResNet18_fpga_accelerator
Users that are interested in ResNet18_fpga_accelerator are comparing it to the libraries listed below
Sorting:
- Nuclei E203 with yolo accelerator based on xc7k325☆14Updated 10 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆48Updated 3 months ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆25Updated 2 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆55Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆107Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆152Updated 2 years ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆76Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆175Updated last year
- ☆111Updated 4 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆178Updated 7 months ago
- ☆61Updated 2 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆40Updated 2 years ago
- ☆10Updated 3 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 4 months ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆28Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆38Updated 10 months ago
- some interesting demos for starters☆81Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆36Updated last year
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆79Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- 使用FPGA实现CNN模型☆15Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆33Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆149Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago