Alternatives and similar repositories for ResNet18_fpga_accelerator:

Users that are interested in ResNet18_fpga_accelerator are comparing it to the libraries listed below

• Zero0Hero / yolo_e203_fpga
  Nuclei E203 with yolo accelerator based on xc7k325
  ☆14Updated 9 months ago
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆45Updated 6 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆98Updated 3 years ago
• bunny965 / yolov5-fpga-hardware-acceleration
  网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR
  ☆101Updated last year
• Futuresxy / General-CNN-Accelerator
  General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
  ☆43Updated last month
• 19801201 / Ultra_low_power_CNN_Accelerated
  ☆10Updated 3 years ago
• FloyedShen / mnist_hls
  Lenet for MNIST handwritten digit recognition using Vivado hls tool
  ☆37Updated 4 years ago
• Xinyang-ZHANG / MNIST
  MNIST using tensorflow, c++ and fpga (zynq7010)
  ☆26Updated 2 years ago
• YutongChenVictor / Fpga-accelerator-demos
  some interesting demos for starters
  ☆76Updated 2 years ago
• matsuda-slab / YOLO_ZYNQ_MASTER
  Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA
  ☆28Updated 3 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆65Updated 2 months ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆47Updated 5 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆169Updated 5 months ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆63Updated 3 months ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆149Updated last year
• xbdxwyh / yolov3_fpga_project
  ☆52Updated 2 years ago
• xiesicong / fpga_sobel_ov5640_hdmi
  fpga跑sobel识别算法
  ☆32Updated 4 years ago
• XueTianyu24 / cnn_accelerator
  【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
  ☆142Updated 2 years ago
• peilin-chen / hls_for_cnn_mnist
  【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码
  ☆74Updated 2 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆43Updated 2 years ago
• doveyour / mnist-nnet-hls-zynq7020-fpga
  to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…
  ☆78Updated 3 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆107Updated 4 years ago
• canteen-man / CNN_FPGA_ZYNQ_PYNQ
  hls code zynq 7020 pynq z2 CNN
  ☆84Updated 6 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆194Updated 2 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆30Updated 4 years ago
• andre1araujo / YOLO-on-PYNQ-Z2
  This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…
  ☆52Updated last month
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆51Updated 3 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆32Updated last year
• OpenHEC / SNN-simulator-on-PYNQcluster
  ☆88Updated 5 years ago