misaleh / CMSIS-DSP-PULPino
CMSIS DSP Library for PULPino microcontroller
☆22Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for CMSIS-DSP-PULPino
- ☆32Updated last year
- Learn NVDLA by SOMNIA☆26Updated 4 years ago
- ☆42Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- ☆37Updated 5 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆62Updated last week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- ☆76Updated last year
- Neural Engine, 16 input channels☆13Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆24Updated last year
- Algorithmic C Math Library☆58Updated 2 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- A scalable Eyeriss model in SystemC.☆23Updated last year
- 关于深度学习算法、框架、编译器、加速器的一些理解☆13Updated 2 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 2 weeks ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 3 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- OpenDLA for trying the demo and FPGA solution☆16Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆25Updated 9 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆30Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- ☆21Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆29Updated this week