misaleh / CMSIS-DSP-PULPinoLinks
CMSIS DSP Library for PULPino microcontroller
☆23Updated 6 years ago
Alternatives and similar repositories for CMSIS-DSP-PULPino
Users that are interested in CMSIS-DSP-PULPino are comparing it to the libraries listed below
Sorting:
- ☆33Updated 2 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Algorithmic C Math Library☆64Updated last month
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆25Updated last week
- This repository contains the results and code for the MLPerf™ Tiny Inference v0.7 benchmark.☆18Updated 2 years ago
- ☆82Updated last year
- Algorithmic C Machine Learning Library☆25Updated 6 months ago
- ☆21Updated 6 years ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- Neural Engine, 16 input channels☆13Updated 2 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆15Updated 2 years ago
- OpenDLA for trying the demo and FPGA solution☆16Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆20Updated 7 years ago
- This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.☆50Updated 4 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆35Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- ☆65Updated last week
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- A scalable Eyeriss model in SystemC.☆28Updated 2 years ago
- Pulp virtual platform☆23Updated 2 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆35Updated last week
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆26Updated 2 years ago
- Aiming at an AI Chip based on RISC-V and NVDLA.☆20Updated 7 years ago