misaleh / CMSIS-DSP-PULPino

Related projects ⓘ

Alternatives and complementary repositories for CMSIS-DSP-PULPino

• pulp-platform / pulp-dsp
  ☆32Updated last year
• pulp-platform / pulp-nn
  ☆77Updated last year
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆26Updated 4 years ago
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆64Updated this week
• pulp-platform / ne16
  Neural Engine, 16 input channels
  ☆13Updated 2 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆66Updated 4 years ago
• pulp-platform / fpu
  ☆37Updated 5 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆23Updated last year
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• sifive / block-nvdla-sifive
  ☆42Updated 3 years ago
• hlslibs / ac_math
  Algorithmic C Math Library
  ☆58Updated 2 months ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆15Updated 3 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆22Updated 3 months ago
• tum-ei-eda / mlonmcu
  Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
  ☆30Updated this week
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆31Updated 3 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆22Updated last year
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆21Updated 2 years ago
• maao666 / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆24Updated 3 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆31Updated last year
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• vrishbhan / Matrix-Multiplication
  Design for 4 x 4 Matrix Multiplication using Verilog
  ☆26Updated 9 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆43Updated 2 years ago
• amohant4 / HLS_for_CNN
  This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
  ☆13Updated 6 years ago
• zeasa / nvdla-compiler
  ☆42Updated 5 years ago