Alternatives and similar repositories for CMSIS-DSP-PULPino

Users that are interested in CMSIS-DSP-PULPino are comparing it to the libraries listed below

• pulp-platform / pulp-nn
  ☆85Updated 2 years ago
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆89Updated 2 months ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆31Updated 2 years ago
• icubecorp / nvdla_compiler
  ☆22Updated 7 years ago
• pulp-platform / pulp-dsp
  ☆35Updated 2 years ago
• IA-C-Lab-Fudan / KWS-SoC
  This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
  ☆53Updated 5 years ago
• zhehaoxu / ai-talk
  关于深度学习算法、框架、编译器、加速器的一些理解
  ☆15Updated 3 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆164Updated 3 years ago
• zeasa / nvdla-compiler
  ☆47Updated 6 years ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆24Updated 6 years ago
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆72Updated 3 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 2 years ago
• dldldlfma / eyeriss_v1
  ☆13Updated 6 years ago
• pulp-platform / pulp-sdk
  ☆121Updated 3 weeks ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆204Updated 5 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆27Updated this week
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• yiwangchunyu / AI-RISC
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆15Updated 4 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆39Updated 5 years ago
• OpenDLA / OpenDLA
  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
  ☆144Updated 8 years ago
• tum-ei-eda / mlonmcu
  Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
  ☆34Updated 2 weeks ago
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆16Updated 6 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆42Updated 5 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 5 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 5 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago