pulp-platform / doryLinks
A tool to deploy Deep Neural Networks on PULP-based SoC's
☆90Updated 4 months ago
Alternatives and similar repositories for dory
Users that are interested in dory are comparing it to the libraries listed below
Sorting:
- ☆85Updated 2 years ago
- NEural Minimizer for pytOrch☆47Updated last year
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆88Updated 2 years ago
- ☆63Updated 5 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆89Updated 2 months ago
- Approximate layers - TensorFlow extension☆26Updated 7 months ago
- Train and deploy LUT-based neural networks on FPGAs☆102Updated last year
- Floating-Point Optimized On-Device Learning Library for the PULP Platform.☆37Updated last month
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆60Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- ☆71Updated 5 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆146Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- ☆35Updated 6 years ago
- CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices☆48Updated 5 years ago
- ☆72Updated 2 years ago
- PyTorch model to RTL flow for low latency inference☆130Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆60Updated last month
- ☆47Updated 6 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆97Updated this week
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆54Updated last year
- ☆40Updated 5 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- DNN Compiler for Heterogeneous SoCs☆55Updated this week
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34Updated 2 weeks ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- NeuraLUT-Assemble☆43Updated 3 months ago
- A collection of tutorials for the fpgaConvNet framework.☆46Updated last year