pulp-platform / llvm-projectLinks
☆12Updated 3 weeks ago
Alternatives and similar repositories for llvm-project
Users that are interested in llvm-project are comparing it to the libraries listed below
Sorting:
- ☆32Updated this week
- RiVEC Bencmark Suite☆123Updated 10 months ago
- Chisel RISC-V Vector 1.0 Implementation☆114Updated 2 weeks ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆109Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- RISC-V Matrix Specification☆22Updated 10 months ago
- ☆37Updated last year
- ☆186Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆153Updated 8 months ago
- Example for running IREE in a bare-metal Arm environment.☆39Updated 2 months ago
- ☆108Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- ☆79Updated last week
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34Updated this week
- Unit tests generator for RVV 1.0☆92Updated 3 weeks ago
- Pulp virtual platform☆24Updated 3 months ago
- ☆17Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆40Updated 4 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆56Updated last week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆42Updated last week
- Vector Acceleration IP core for RISC-V*☆184Updated 5 months ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆87Updated 2 weeks ago
- ☆61Updated this week
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Example of RISC-V Vector programming☆25Updated last month
- PyTorch model to RTL flow for low latency inference☆130Updated last year