Alternatives and similar repositories for llvm-project

Users that are interested in llvm-project are comparing it to the libraries listed below

• gvsoc / gvsoc
  ☆37Updated last week
• tum-ei-eda / mlonmcu
  Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
  ☆32Updated last week
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆40Updated 6 months ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆44Updated 5 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆83Updated 7 years ago
• riscv / riscv-bfloat16
  ☆38Updated last year
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆118Updated 2 years ago
• THU-DSP-LAB / llvm-project
  LLVM OpenCL C compiler suite for ventus GPGPU
  ☆58Updated last month
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• StanfordAHA / aha
  ☆62Updated this week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆127Updated last year
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆91Updated 4 months ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆131Updated 4 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆141Updated last week
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆79Updated last month
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆288Updated last year
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆166Updated 2 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 2 months ago
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆44Updated last year
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆161Updated 11 months ago
• embecosm / embecosm-toolchain-releases
  ☆17Updated last month
• Xilinx / mlir-air
  ☆123Updated this week
• rivosinc / veclibm
  Vector math library using RISC-V vector ISA via C intrinsic
  ☆24Updated 3 weeks ago
• TeCSAR-UNCC / gem5-SALAM
  ☆109Updated last year
• pulp-platform / redmule
  ☆90Updated this week
• Xilinx / hls-llvm-project
  ☆40Updated 3 months ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆31Updated last month