hossein1387 / BARVINN
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
☆81Updated 2 weeks ago
Alternatives and similar repositories for BARVINN:
Users that are interested in BARVINN are comparing it to the libraries listed below
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆69Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 3 weeks ago
- Basic floating-point components for RISC-V processors☆63Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆98Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆119Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆155Updated 3 weeks ago
- ☆102Updated 11 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆84Updated this week
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆47Updated 5 months ago
- PYNQ Composabe Overlays☆69Updated 7 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆42Updated 4 years ago
- ☆83Updated 7 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆157Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆62Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- Vector processor for RISC-V vector ISA☆112Updated 4 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆50Updated last month
- Pure digital components of a UCIe controller☆50Updated this week
- ☆147Updated 9 months ago
- ☆26Updated 5 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago
- IC implementation of TPU☆92Updated 5 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆153Updated this week
- Open-Source HLS Examples for Microchip FPGAs☆40Updated last month
- ☆50Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆65Updated last year
- ☆80Updated 9 months ago
- DNN Compiler for Heterogeneous SoCs☆20Updated this week
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆112Updated last year