hossein1387 / BARVINNView external linksLinks
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
☆94Jan 5, 2025Updated last year
Alternatives and similar repositories for BARVINN
Users that are interested in BARVINN are comparing it to the libraries listed below
Sorting:
- A Barrel design of RV32I☆22Jul 30, 2023Updated 2 years ago
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 7 months ago
- ☆16Jul 1, 2024Updated last year
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 4 years ago
- ☆90Updated this week
- ☆89Oct 18, 2023Updated 2 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- ☆38Oct 21, 2025Updated 3 months ago
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆105Feb 22, 2023Updated 2 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Neural Network Quantization With Fractional Bit-widths☆11Feb 19, 2021Updated 4 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 3 years ago
- A Verilog parser for Haskell.☆36Jul 6, 2021Updated 4 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆19Jan 21, 2022Updated 4 years ago
- ☆60Aug 30, 2021Updated 4 years ago
- EVEREST: e-Versatile Research Stick for peoples☆36Apr 12, 2023Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- ☆91Oct 13, 2025Updated 4 months ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆17Apr 6, 2022Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28May 11, 2022Updated 3 years ago
- An open-source custom cache generator.☆34Mar 14, 2024Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 5 years ago
- FPGA implementation of the AnotherWorld CPU (equivalent to the original VM)☆16Apr 6, 2020Updated 5 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- ☆32Mar 31, 2025Updated 10 months ago
- TinyTapeout-01 submission repo☆32Nov 28, 2022Updated 3 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆402Feb 6, 2026Updated last week