sifive / block-nvdla-sifive
☆42Updated 3 years ago
Alternatives and similar repositories for block-nvdla-sifive:
Users that are interested in block-nvdla-sifive are comparing it to the libraries listed below
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆64Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- ☆15Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 5 months ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 5 years ago
- SoCRocket - Core Repository☆34Updated 7 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆41Updated 6 years ago
- A repository for SystemC Learning examples☆65Updated 2 years ago
- Tutorials on HLS Design☆51Updated 5 years ago
- ☆42Updated this week
- ☆77Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆85Updated 2 years ago
- ☆21Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Archives of SystemC from The Ground Up Book Exercises☆30Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆90Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week