Pulp virtual platform
☆24Jul 16, 2025Updated last year
Alternatives and similar repositories for gvsoc
Users that are interested in gvsoc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆44Updated this week
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆95Aug 4, 2025Updated 11 months ago
- ☆127Apr 20, 2026Updated 3 months ago
- ☆27Jan 30, 2026Updated 5 months ago
- ☆107Aug 19, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- CV32E40X Design-Verification environment☆16Jun 2, 2026Updated last month
- Development and simulation framework for Application Specific Vector Processor☆16Mar 8, 2020Updated 6 years ago
- ☆12Updated this week
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Sep 16, 2019Updated 6 years ago
- A risc-v simulator based on SystrmC☆14Jan 7, 2022Updated 4 years ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆16Jun 29, 2026Updated 3 weeks ago
- mi-optimize is a versatile tool designed for the quantization and evaluation of large language models (LLMs). The library's seamless inte…☆25Nov 28, 2024Updated last year
- ☆13Jan 14, 2021Updated 5 years ago
- ☆14Apr 28, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- MatchLib Connections Toolkit - example designs leveraging Connections☆16Jul 6, 2026Updated 2 weeks ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆37Dec 24, 2024Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- A gdbstub for connecting GDB to a RISC-V Debug Module☆29Oct 7, 2024Updated last year
- ☆16Jun 17, 2025Updated last year
- A 5-stage pipelining RISC-V 32I simulator written in Rust.☆19Apr 21, 2021Updated 5 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 2 years ago
- An Eclipse 4 RCP based GUI to interact with SystemC simulators☆15Mar 19, 2026Updated 4 months ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆13Feb 22, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Aug 30, 2016Updated 9 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- ☆41Mar 5, 2024Updated 2 years ago
- Information Bottleneck in DNN with PyTorch☆15Jul 6, 2023Updated 3 years ago
- RISC-V Virtual Prototype☆49Oct 1, 2021Updated 4 years ago
- Various test models in WNNX format. It can view with `pip install wnetron && wnetron`☆12Jun 22, 2022Updated 4 years ago
- A flexible event-driven cycle-accurate network simulator☆28Jan 28, 2020Updated 6 years ago
- Tool to connect the workstation to the pulp targets abd interact with them☆11Oct 22, 2020Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- LimeSDR with Matlab☆11Dec 30, 2019Updated 6 years ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆16Jul 2, 2026Updated 2 weeks ago
- A simple utility for doing RISC-V HPM perf monitoring.☆18May 8, 2017Updated 9 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆70Jul 10, 2026Updated last week
- Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.☆14Nov 29, 2018Updated 7 years ago
- ☆15Mar 28, 2026Updated 3 months ago
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year