pulp-platform / gvsocLinks
Pulp virtual platform
☆23Updated 2 months ago
Alternatives and similar repositories for gvsoc
Users that are interested in gvsoc are comparing it to the libraries listed below
Sorting:
- ☆32Updated this week
- ☆73Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆108Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated last month
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- Learn NVDLA by SOMNIA☆42Updated 5 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆35Updated 2 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆108Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- ☆84Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 2 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Simple runtime for Pulp platforms☆49Updated 3 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- Next generation CGRA generator☆114Updated this week
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆61Updated 8 months ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 8 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated 3 months ago
- Intel Compiler for SystemC☆24Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago