ahmad-mirsalari / PULPLinks
A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.
☆28Updated last month
Alternatives and similar repositories for PULP
Users that are interested in PULP are comparing it to the libraries listed below
Sorting:
- A Fast, Low-Overhead On-chip Network☆257Updated 3 weeks ago
- A demo system for Ibex including debug support and some peripherals☆85Updated 2 months ago
- 2D Systolic Array Multiplier☆23Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆233Updated last week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆102Updated this week
- BlackParrot on Zynq☆47Updated 3 weeks ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 3 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆71Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL☆56Updated 5 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆99Updated 6 months ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆183Updated this week
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- whatever it means☆15Updated 3 weeks ago
- SystemVerilog Tutorial☆186Updated last month
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆69Updated last year
- This is a tutorial on standard digital design flow☆82Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated 2 months ago
- An AXI4 crossbar implementation in SystemVerilog☆201Updated 4 months ago
- ☆40Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆141Updated 7 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆129Updated 2 years ago