ahmad-mirsalari / PULP
A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.
☆21Updated last year
Alternatives and similar repositories for PULP:
Users that are interested in PULP are comparing it to the libraries listed below
- ☆31Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆42Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆69Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆164Updated 4 months ago
- ai_accelerator_basic_for_student (no solve)☆12Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆63Updated 3 months ago
- A verilog implementation for Network-on-Chip☆72Updated 7 years ago
- General Purpose AXI Direct Memory Access☆48Updated 10 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆51Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆186Updated this week
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated 2 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- This is a tutorial on standard digital design flow☆75Updated 3 years ago
- Vector processor for RISC-V vector ISA☆116Updated 4 years ago
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated 3 weeks ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆43Updated 9 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆51Updated 7 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆89Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆125Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- A collection of commonly asked RTL design interview questions☆26Updated 7 years ago
- 2D Systolic Array Multiplier☆12Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆141Updated last month