ahmad-mirsalari / PULP
A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.
☆21Updated last year
Alternatives and similar repositories for PULP:
Users that are interested in PULP are comparing it to the libraries listed below
- ☆31Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Two Level Cache Controller implementation in Verilog HDL☆43Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆55Updated last month
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A Fast, Low-Overhead On-chip Network☆197Updated this week
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated last week
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆24Updated 6 years ago
- ai_accelerator_basic_for_student (no solve)☆12Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆50Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated 2 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆74Updated this week
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆16Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 5 years ago
- ☆63Updated 6 years ago
- Advanced Architecture Labs with CVA6☆58Updated last year
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- This is a tutorial on standard digital design flow☆75Updated 3 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆44Updated 9 months ago