EEESlab / CMSIS_NN-INTQLinks
INT-Q Extension of the CMSIS-NN library for ARM Cortex-M target
☆18Updated 6 years ago
Alternatives and similar repositories for CMSIS_NN-INTQ
Users that are interested in CMSIS_NN-INTQ are comparing it to the libraries listed below
Sorting:
- CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices☆48Updated 5 years ago
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆93Updated 6 months ago
- ☆35Updated 6 years ago
- Mobilenet v1 trained on Imagenet for STM32 using extended CMSIS-NN with INT-Q quantization support☆91Updated 5 years ago
- ☆30Updated 6 years ago
- ☆40Updated 6 years ago
- μNAS is a neural architecture search (NAS) system that designs small-yet-powerful microcontroller-compatible neural networks.☆82Updated 5 years ago
- ☆65Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆148Updated 6 years ago
- This repository containts the pytorch scripts to train mixed-precision networks for microcontroller deployment, based on the memory contr…☆50Updated last year
- ☆20Updated last year
- This repository contains the results and code for the MLPerf™ Tiny Inference v0.7 benchmark.☆19Updated 2 years ago
- Jupyter notebook examples on image classification with quantized neural networks☆71Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆29Updated last year
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆32Updated 2 weeks ago
- A library to train and deploy quantised Deep Neural Networks☆26Updated last year
- BNNs (XNOR, BNN and DoReFa) implementation for PyTorch 1.0+☆40Updated 2 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Train and deploy LUT-based neural networks on FPGAs☆106Updated last year
- ☆71Updated 5 years ago
- Verilog and Python drivers and APIs for Neurram 48-core chip☆44Updated 3 years ago
- ☆89Updated 2 years ago
- Generate an FPGA design for a TWN☆10Updated 6 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆32Updated last year
- An LSTM template and a few examples using Vivado HLS☆47Updated last year
- This project implements a convolution kernel based on vivado HLS on zcu104