The PULP RI5CY core modified for Verilator modeling and as a GDB server.
☆28Jan 11, 2019Updated 7 years ago
Alternatives and similar repositories for ri5cy
Users that are interested in ri5cy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆15Jan 17, 2025Updated last year
- GPGPU-SIM 使用篇☆14Nov 12, 2022Updated 3 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆20Aug 14, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 3 years ago
- RISCV lock-step checker based on Spike☆16Sep 20, 2026Updated last month
- personal practice☆11Sep 18, 2026Updated last month
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- Generative Benchmark for LLM-Aided Hardware Design☆30Jun 4, 2025Updated last year
- Public release☆60Sep 3, 2019Updated 7 years ago
- ☆42Dec 8, 2024Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆35Apr 13, 2021Updated 5 years ago
- My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA☆13Jun 26, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆24Sep 12, 2021Updated 5 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 12 years ago
- CORE-V MCU UVM Environment and Test Bench☆29Jul 19, 2024Updated 2 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- A set of tools that automate the execution of scarab simulations☆21Updated this week
- ☆15Sep 27, 2022Updated 4 years ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,320Updated this week
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆39Jun 7, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆41Dec 4, 2020Updated 5 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆29Nov 21, 2019Updated 6 years ago
- Verilog PCI express components☆28Jun 26, 2023Updated 3 years ago
- A time-predictable processor for mixed-criticality systems☆64Nov 7, 2024Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- Hack@DAC 2021☆21Jul 24, 2024Updated 2 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆24May 11, 2021Updated 5 years ago
- RTL generator for SpGEMM☆13Feb 2, 2021Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- ☆100Oct 18, 2023Updated 3 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago