The PULP RI5CY core modified for Verilator modeling and as a GDB server.
☆27Jan 11, 2019Updated 7 years ago
Alternatives and similar repositories for ri5cy
Users that are interested in ri5cy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆15Jan 17, 2025Updated last year
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- This repo contain the PY-UVM Framework for different RISC-V Cores☆33Sep 16, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- ☆41Dec 8, 2024Updated last year
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- ☆18Apr 18, 2024Updated 2 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆19Aug 27, 2025Updated 11 months ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 6 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Apr 28, 2026Updated 3 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆97Oct 18, 2023Updated 2 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- A ZipCPU based demonstration of the MAX1000 FPGA board☆24May 11, 2021Updated 5 years ago
- GPGPU-SIM 使用篇☆14Nov 12, 2022Updated 3 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- Hack@DAC 2021☆20Jul 24, 2024Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An implementation of unsupervised example of the Forward-Forward algorithm proposed by (Hinton, 2022)☆10Jun 19, 2024Updated 2 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- ZPU Core for Lattice ICE40HX8K☆12Apr 26, 2014Updated 12 years ago
- Mirrors of the Accellera UVM Reference Implementations at https://www.accellera.org/downloads/standards/uvm.☆16Aug 23, 2021Updated 4 years ago
- ☆15Jul 28, 2022Updated 4 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Jan 26, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆30Mar 13, 2025Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆59May 10, 2021Updated 5 years ago
- Clarvi simple RISC-V processor for teaching☆58Aug 25, 2017Updated 8 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,269May 29, 2026Updated 2 months ago
- ☆19Jul 9, 2026Updated 2 weeks ago
- ☆17May 29, 2023Updated 3 years ago
- ☆13May 5, 2023Updated 3 years ago