embecosm / ri5cyLinks
The PULP RI5CY core modified for Verilator modeling and as a GDB server.
☆23Updated 6 years ago
Alternatives and similar repositories for ri5cy
Users that are interested in ri5cy are comparing it to the libraries listed below
Sorting:
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆29Updated last month
- Development of a Network on Chip Simulation using SystemC.☆32Updated 7 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 8 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 5 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆55Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- ☆49Updated 6 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆35Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated last month
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated last year
- SRAM☆22Updated 4 years ago
- Platform Level Interrupt Controller☆40Updated last year
- BlackParrot on Zynq☆41Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 months ago
- ☆27Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated last year
- ☆58Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆67Updated last week
- Reconfigurable Binary Engine☆16Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆28Updated last year
- StateMover is a checkpoint-based debugging framework for FPGAs.☆19Updated 2 years ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- Modular Multi-ported SRAM-based Memory☆29Updated 6 months ago