grayresearch / s4gaLinks
a small simple slow serial FPGA core
☆16Updated 4 years ago
Alternatives and similar repositories for s4ga
Users that are interested in s4ga are comparing it to the libraries listed below
Sorting:
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- ☆33Updated 3 years ago
- ☆34Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆48Updated last week
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated last year
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- Generate Zynq configurations without using the vendor GUI☆30Updated 2 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- PCIe analyzer experiments☆63Updated 5 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- ☆38Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated this week
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆46Updated 3 weeks ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆92Updated 5 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Virtual Development Board☆64Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆38Updated 11 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year