grayresearch / s4ga
a small simple slow serial FPGA core
☆16Updated 4 years ago
Alternatives and similar repositories for s4ga:
Users that are interested in s4ga are comparing it to the libraries listed below
- ☆33Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆41Updated last month
- FPGA board-level debugging and reverse-engineering tool☆36Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆32Updated 4 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated last month
- USB virtual model in C++ for Verilog☆29Updated 6 months ago
- S3GA: a simple scalable serial FPGA☆10Updated 2 years ago
- Small footprint and configurable HyperBus core☆11Updated 2 years ago
- ☆33Updated 4 years ago
- A padring generator for ASICs☆25Updated last year
- This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.☆10Updated 3 years ago
- Virtual development board for HDL design☆41Updated 2 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Generic Logic Interfacing Project☆45Updated 4 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated last week
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- ☆22Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- PicoRV☆44Updated 5 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆28Updated 2 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆27Updated 6 months ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- RISC-V processor☆29Updated 2 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 weeks ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year