fabianschuiki / potstill
An open source generator for standard cell based memories.
☆13Updated 8 years ago
Alternatives and similar repositories for potstill:
Users that are interested in potstill are comparing it to the libraries listed below
- fakeram generator for use by researchers who do not have access to commercial ram generators☆36Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- ☆31Updated 4 months ago
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Python interface for cross-calling with HDL☆32Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- Open source process design kit for 28nm open process☆55Updated last year
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆27Updated last week
- SRAM☆22Updated 4 years ago
- An automatic clock gating utility☆47Updated 3 weeks ago
- ☆36Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 7 months ago
- ☆40Updated 3 years ago
- BAG framework☆40Updated 9 months ago
- ☆37Updated last month
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆40Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 4 years ago
- ☆44Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- Library of open source Process Design Kits (PDKs)☆39Updated last week
- ☆31Updated last year
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 4 months ago
- A configurable SRAM generator☆48Updated 4 months ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆44Updated 4 years ago