LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
☆21Oct 22, 2025Updated 8 months ago
Alternatives and similar repositories for len5
Users that are interested in len5 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Unified RISC-V Access Platform (UAP) project repository☆27Jun 11, 2026Updated last month
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆16Nov 12, 2025Updated 8 months ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆285Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆90Apr 1, 2026Updated 3 months ago
- ☆146Jun 8, 2026Updated last month
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆21May 8, 2025Updated last year
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- ☆23Apr 24, 2026Updated 2 months ago
- RISC-V Nox core☆72Jul 22, 2025Updated 11 months ago
- A C++ neural network library for machine learning☆16May 1, 2024Updated 2 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CVA6 SDK containing RISC-V tools and Buildroot☆80Mar 27, 2026Updated 3 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- FuseSoC standard core library☆166Apr 28, 2026Updated 2 months ago
- ☆19Jul 26, 2024Updated last year
- APB Timer Unit☆14Oct 30, 2025Updated 8 months ago
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 4 years ago
- matrix-coprocessor for RISC-V☆36Feb 27, 2026Updated 4 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆59May 10, 2021Updated 5 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 6 months ago
- ☆11Mar 12, 2024Updated 2 years ago
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 9 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated 2 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- RISC-V(RV32IM) emulator with support for syscalls.☆30Oct 4, 2023Updated 2 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 4 years ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆16Jul 2, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year
- ☆15Jul 5, 2019Updated 7 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆16Oct 15, 2016Updated 9 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆20Jan 29, 2026Updated 5 months ago