Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
☆15Mar 31, 2026Updated 2 weeks ago
Alternatives and similar repositories for open-register-design-tool
Users that are interested in open-register-design-tool are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 5 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- Download proccedings from DVCon☆24Mar 29, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Jun 27, 2023Updated 2 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆112Oct 31, 2023Updated 2 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆12Jan 15, 2017Updated 9 years ago
- Medium Access Control layer of 802.15.4☆12Nov 14, 2014Updated 11 years ago
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 6 years ago
- ☆27Mar 25, 2019Updated 7 years ago
- Program to scan for malicious FPGA designs.☆17Mar 20, 2021Updated 5 years ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- CMake/GoogleTest/TravisCI/Coveralls/CoverityScan/Doxygen☆10Aug 8, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- opensource crypto IP core☆30Nov 20, 2020Updated 5 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- JSON lib in Systemverilog☆44Feb 23, 2022Updated 4 years ago
- phpLicenseWatcher is a simple Web frontend to the FlexLM lmstat and lmdiag commands that gives information about the status of FlexLM ser…☆42Jan 26, 2026Updated 2 months ago
- Use C with sphinx.ext.autodoc☆14Apr 8, 2026Updated last week
- SystemRDL 2.0 language compiler front-end☆275Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆78Mar 28, 2026Updated 2 weeks ago
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆11Sep 2, 2016Updated 9 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 10 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 2 months ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 4 years ago
- PCIe adapter for an FPGA accelerator for Open CloudServer☆25May 31, 2020Updated 5 years ago
- Yet Another Simulation Architecture☆80Sep 17, 2020Updated 5 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 6 years ago
- SpringMVC + Hibernate + Shiro 个人博客☆15Aug 28, 2017Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A SystemVerilog source file pickler.☆61Oct 20, 2024Updated last year
- RISC-V CSR Access Routines☆16Dec 27, 2022Updated 3 years ago
- Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)☆23Aug 2, 2021Updated 4 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆46Jun 13, 2023Updated 2 years ago
- An Ethernet MAC conforming to IEEE 802.3☆24May 13, 2017Updated 8 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago