sdnellen / open-register-design-toolView external linksLinks
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
☆15Dec 19, 2024Updated last year
Alternatives and similar repositories for open-register-design-tool
Users that are interested in open-register-design-tool are comparing it to the libraries listed below
Sorting:
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 3 months ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆12Jan 15, 2017Updated 9 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Nov 22, 2019Updated 6 years ago
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 6 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Aug 1, 2019Updated 6 years ago
- ☆25Mar 25, 2019Updated 6 years ago
- Download proccedings from DVCon☆22Jun 9, 2021Updated 4 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆23Apr 24, 2021Updated 4 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆74Dec 12, 2025Updated 2 months ago
- opensource crypto IP core☆29Nov 20, 2020Updated 5 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- AXI4 BFM in Verilog☆35Dec 13, 2016Updated 9 years ago
- phpLicenseWatcher is a simple Web frontend to the FlexLM lmstat and lmdiag commands that gives information about the status of FlexLM ser…☆42Jan 26, 2026Updated 2 weeks ago
- ☆12Aug 26, 2016Updated 9 years ago
- Build and test environment for CMSIS-Pack containing TensorFlow Lite Micro☆17Jul 9, 2025Updated 7 months ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- ☆41Apr 4, 2021Updated 4 years ago
- Medium Access Control layer of 802.15.4☆13Nov 14, 2014Updated 11 years ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- SystemRDL 2.0 language compiler front-end☆271Jan 16, 2026Updated 3 weeks ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Bootloader tool for OLS☆22Jul 17, 2016Updated 9 years ago
- JSON lib in Systemverilog☆44Feb 23, 2022Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Aug 10, 2022Updated 3 years ago
- PCB layout for my cheap FPGA HDMI experimenting board☆10Aug 21, 2014Updated 11 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- Port of Brian Bennet's NES Emulator for the second generation Panologic thin client☆13Apr 21, 2022Updated 3 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- ☆12Sep 8, 2017Updated 8 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- USB serial device (CDC-ACM)☆44Jun 28, 2020Updated 5 years ago
- hjson-formatter☆12Apr 26, 2021Updated 4 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Mar 10, 2019Updated 6 years ago
- Demo project for CoIDE to use the USB peripheral of Nucleo F401 board as USB host or device with Mass Storage Class.☆10Dec 3, 2014Updated 11 years ago
- Light implementation of boxee.tv server to restore functionality to Boxee Boxes☆10Dec 17, 2023Updated 2 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆11Apr 2, 2025Updated 10 months ago