☆19Aug 30, 2020Updated 5 years ago
Alternatives and similar repositories for vhdl2verilog
Users that are interested in vhdl2verilog are comparing it to the libraries listed below
Sorting:
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated 3 weeks ago
- Xilinx CPLD replacement for the Commodore Amiga Amber custom chip☆14Oct 31, 2025Updated 4 months ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- Icarus SIMBUS☆20Nov 6, 2019Updated 6 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated 7 months ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Nov 2, 2025Updated 4 months ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin☆21Aug 8, 2022Updated 3 years ago
- ☆20Aug 4, 2022Updated 3 years ago
- general-cores☆21Jul 16, 2025Updated 7 months ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated last month
- A reconfigurable logic circuit made of identical rotatable tiles.☆24Nov 15, 2021Updated 4 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆26Sep 9, 2025Updated 5 months ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- ☆12May 21, 2024Updated last year
- KLayout technology files for FreePDK45☆23Jun 12, 2021Updated 4 years ago
- ☆140Feb 16, 2026Updated 2 weeks ago
- KLayout technology files for ASAP7 FinFET educational process☆25Feb 5, 2023Updated 3 years ago
- Low level arithmetic primitives in RTL☆23Apr 3, 2020Updated 5 years ago
- ☆23Mar 15, 2025Updated 11 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Verilog development and verification project for HOL4☆28Apr 25, 2025Updated 10 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- ABC: System for Sequential Logic Synthesis and Formal Verification☆32Updated this week
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- a finite element in geotechnical applications☆17Nov 21, 2024Updated last year
- VHDL for basic floating-point operations.☆31Oct 2, 2018Updated 7 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 3 months ago
- ☆33Jan 7, 2025Updated last year
- ☆11Apr 3, 2017Updated 8 years ago
- Release version 0.2 of OpenFcst☆16Apr 8, 2015Updated 10 years ago
- ☆11Oct 10, 2018Updated 7 years ago
- gpvdm☆11Apr 7, 2022Updated 3 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Oct 16, 2017Updated 8 years ago