RISC-V soft-core PEs for TaPaSCo
☆23Jan 30, 2026Updated 3 months ago
Alternatives and similar repositories for tapasco-riscv
Users that are interested in tapasco-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Fault Injection Automatic Test Equipment☆15Nov 22, 2021Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- ☆14Feb 24, 2025Updated last year
- GSI Timing Gateware and Tools☆14Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 6-stage dual-issue in-order superscalar risc-v cpu☆14May 2, 2026Updated last week
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Jan 16, 2026Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆131Jul 11, 2025Updated 9 months ago
- The Repository contains the code of various Digital Circuits☆12Aug 7, 2023Updated 2 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 3 months ago
- ☆15Jul 5, 2019Updated 6 years ago
- general-cores☆21Jul 16, 2025Updated 9 months ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆21Jul 18, 2019Updated 6 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 5 months ago
- Instruction decoder microbenchmark suite☆11Oct 31, 2017Updated 8 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Feb 1, 2017Updated 9 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- This is a repository whose core is in its Wiki page https://github.com/caprivm/virtualization/wiki. The repository, which I'm going to ca…☆11Jan 22, 2024Updated 2 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- The Task Parallel System Composer (TaPaSCo)☆126Apr 29, 2026Updated last week
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆19Sep 2, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Sep 9, 2025Updated 8 months ago
- ☆11Jan 2, 2026Updated 4 months ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- AXI4 with a FIFO integrated with VIP☆24Feb 29, 2024Updated 2 years ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated last month
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆24Oct 1, 2022Updated 3 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆28Jul 17, 2025Updated 9 months ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Mar 29, 2013Updated 13 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆73Updated this week
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago