CAN with Flexible Data-rate IP Core developed at Department of Measurement of FEE CTU
☆34Sep 15, 2022Updated 3 years ago
Alternatives and similar repositories for ctucanfd_ip_core
Users that are interested in ctucanfd_ip_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 6 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆19May 12, 2026Updated last week
- SocketCAN Linux driver for UAB "Rusoku Technologies" TouCAN USB to CAN bus converter☆10Sep 4, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V by VectorBlox☆11Jul 19, 2017Updated 8 years ago
- Simulink Embedded Coder target for Linux☆31Apr 26, 2022Updated 4 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- Very Simple Control Protocol (VSCP) Level 1 Framework☆11May 11, 2026Updated last week
- utilizing TJA1020 Lin-Transceiver☆15Oct 7, 2024Updated last year
- TwoCan is an OpenCPN PlugIn for integrating OpenCPN with NMEA2000® networks☆11Jun 23, 2025Updated 10 months ago
- Collection of Raspberry Pi Pico board adapters for use with Pico-DirtyJTAG☆15Jun 5, 2024Updated last year
- Small example demonstrating overlay windows with accessibility service on Android.☆11Apr 22, 2021Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 6 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 3 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆14Jan 21, 2022Updated 4 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- collection of esp32 libraries☆11Aug 9, 2018Updated 7 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- Baseband Receiver IP for GPS like DSSS signals☆41May 19, 2020Updated 6 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Jan 25, 2022Updated 4 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 5 years ago
- Mirror of the now discontinued ORCA RISC-V processor from VectorBlox.☆11Feb 11, 2020Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Nov 1, 2020Updated 5 years ago
- Network protocol libraries for VHDL test benches☆13Mar 9, 2026Updated 2 months ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- LED blink example design for the Arrow DECA FPGA board☆16Jul 30, 2021Updated 4 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 3 months ago
- An experimental package manager and development tool for Hardware Description Languages (HDL).☆14Apr 10, 2022Updated 4 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Novo Bus Analyzer is a fork of BUSMASTER. BUSMASTER is an Open Source Software tool to simulate, analyze and test data bus systems such a…☆16Mar 21, 2025Updated last year
- A ROS 2 package integrating the Soar cognitive architecture into the ROS ecosystem.☆19Apr 26, 2026Updated 3 weeks ago
- Doppler effect on WaveForms☆17Sep 1, 2025Updated 8 months ago
- ROS node for triggering cameras using GPIO on Jetson (targeting ROSCubeX, but easily adaptable to other platforms)☆13Updated this week
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 9 years ago
- An ultrasonic water flowmeter based on transit-time technique☆17Jul 21, 2021Updated 4 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆47Nov 24, 2025Updated 5 months ago