Alternatives and similar repositories for dma-driver:

Users that are interested in dma-driver are comparing it to the libraries listed below

• corundum / verilog-pcie
  Verilog PCI express components
  ☆22Updated last year
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆20Updated 4 years ago
• acsl-technion / ntl
  Networking Template Library for Vivado HLS
  ☆28Updated 4 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆17Updated 5 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆46Updated 4 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• beehive-lab / FastPath_MP
  FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
  ☆32Updated 3 years ago
• DUNE / pl-nvme
  ☆29Updated 4 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆53Updated 2 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• UCLA-VAST / HT-Deflate-FPGA
  ☆14Updated 2 years ago
• rsarwar87 / xdma_dsc_byp_cltr
  VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe
  ☆15Updated 5 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆25Updated 5 years ago
• strezh / XPDMA
  PCIe DMA Subsystem based on Xilinx XAPP1171
  ☆45Updated last year
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆16Updated 7 months ago
• slaclab / axi-pcie-core
  ☆21Updated this week
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆22Updated 6 years ago
• FDU-ME-ARC / NVMeCHA
  ☆14Updated 3 years ago
• fpgasystems / Centaur
  Centaur, a framework for hybrid CPU-FPGA databases
  ☆27Updated 7 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆43Updated last month
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆33Updated last year
• ucb-ee290c / fa18-smartnic
  SmartNIC
  ☆14Updated 6 years ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• RSPwFPGAs / virtio-fpga-bridge
  Virtio front-end and back-end bridge, implemented with FPGA.
  ☆28Updated 4 years ago
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆47Updated 7 years ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆15Updated 5 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 9 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆23Updated last month