hellgate202 / crc_calcLinks
Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
☆14Updated 6 years ago
Alternatives and similar repositories for crc_calc
Users that are interested in crc_calc are comparing it to the libraries listed below
Sorting:
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Wishbone SATA Controller☆19Updated 2 months ago
- APB Logic☆19Updated 3 weeks ago
- Generic AXI master stub☆19Updated 11 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- ☆21Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- Open FPGA Modules☆24Updated 10 months ago
- ☆16Updated 6 years ago
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆28Updated 9 years ago
- Computational Storage Device based on the open source project OpenSSD.☆27Updated 4 years ago
- ☆21Updated last month
- ☆32Updated last year
- Xilinx IP repository☆13Updated 7 years ago
- hdmi-ts Project☆13Updated 8 years ago
- ☆21Updated 5 years ago
- Open-Channel Open-Way Flash Controller☆17Updated 3 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- LIS Network-on-Chip Implementation☆31Updated 8 years ago
- ESnet general-purpose FPGA design library.☆13Updated 2 weeks ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 7 months ago
- LMAC Core1 - Ethernet 1G/100M/10M☆17Updated 2 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- ☆30Updated last week
- ☆18Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆16Updated 3 years ago