Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
☆15Apr 11, 2019Updated 7 years ago
Alternatives and similar repositories for crc_calc
Users that are interested in crc_calc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 8 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆40Aug 5, 2020Updated 5 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- Building a simple oscilloscope using FPGA board and PCB.☆22Dec 30, 2020Updated 5 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Dec 16, 2019Updated 6 years ago
- FPGA Based GPS Synchronized Clock☆10May 7, 2021Updated 5 years ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆16Aug 29, 2022Updated 3 years ago
- A min-sum LDPC decoder written in SystemVerilog (IEEE 1800-2012)☆13Jan 8, 2021Updated 5 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A multiply core generator☆16Jun 25, 2020Updated 6 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆17May 21, 2014Updated 12 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- All switching software as well as control software for a physically and emulated capable network coding switch. FPGA Acceleration added .…☆10Nov 19, 2019Updated 6 years ago
- USB capture IP☆26Jun 6, 2020Updated 6 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- ☆21Dec 9, 2018Updated 7 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆25Nov 7, 2018Updated 7 years ago
- ☆16Mar 18, 2024Updated 2 years ago
- ☆15Jul 5, 2019Updated 7 years ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 5 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆22Updated this week
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 6 months ago
- ☆46Apr 11, 2017Updated 9 years ago
- APB Logic☆26Jul 2, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year
- FPGA Projects written using SystemVerilog, Verilog, and VHDL are put here in seperate folders.☆19Apr 26, 2017Updated 9 years ago
- KVM over IP Gateway targeting Zynq-7000 SoC☆21Mar 5, 2022Updated 4 years ago
- An FPGA-based NetTLP adapter☆29Mar 10, 2020Updated 6 years ago
- Video Stream Scaler☆42Jul 17, 2014Updated 12 years ago
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Apr 15, 2018Updated 8 years ago