hellgate202 / crc_calcLinks
Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
☆15Updated 6 years ago
Alternatives and similar repositories for crc_calc
Users that are interested in crc_calc are comparing it to the libraries listed below
Sorting:
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- Open FPGA Modules☆24Updated last year
- Generic AXI master stub☆19Updated 11 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- ☆21Updated 5 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 10 months ago
- ☆22Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- Wishbone SATA Controller☆23Updated 2 months ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- ☆16Updated 6 years ago
- Verification IP for Watchdog☆12Updated 4 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- APB Logic☆22Updated last month
- Computational Storage Device based on the open source project OpenSSD.☆29Updated 5 years ago
- ☆30Updated 8 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Updated 2 years ago
- ☆35Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- ☆16Updated 4 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- ☆28Updated 5 months ago
- Testbenches for HDL projects☆22Updated last week
- AXI X-Bar☆19Updated 5 years ago