☆15Jul 5, 2019Updated 7 years ago
Alternatives and similar repositories for apb_uart_sv
Users that are interested in apb_uart_sv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AXI4 with a FIFO integrated with VIP☆25Feb 29, 2024Updated 2 years ago
- ☆52Nov 3, 2023Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- ☆26Oct 8, 2019Updated 6 years ago
- AHB to APB Bridge VIP☆30Mar 4, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- UART 16550 core☆43Jul 17, 2014Updated 12 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆21Sep 2, 2023Updated 2 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- RISC-V soft-core PEs for TaPaSCo☆24Jul 24, 2026Updated 2 weeks ago
- APB to I2C☆44Jul 17, 2014Updated 12 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 3 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- ☆21Dec 9, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆21Nov 18, 2022Updated 3 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 9 months ago
- Linrad - SDR receiver☆19Nov 22, 2025Updated 8 months ago
- RISC-V Core Local Interrupt Controller (CLINT)☆33Updated this week
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- APB Logic☆29Updated this week
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Feb 23, 2020Updated 6 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Repository for holding all CCSDS MO Training documentation, examples, tutorials and issue lists☆14Jul 30, 2019Updated 7 years ago
- SPI Master Core clone from OpenCores☆14Oct 4, 2013Updated 12 years ago
- ☆19Updated this week
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆138Nov 29, 2017Updated 8 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆12Feb 19, 2022Updated 4 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆38Jun 16, 2026Updated last month
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- VCD Parser for Node.js☆11Jan 7, 2023Updated 3 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆72Feb 21, 2020Updated 6 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆80Dec 11, 2023Updated 2 years ago
- Diff3DHPE: A Diffusion Model for 3D Human Pose Estimation [R6D 2023] [Official]☆15May 23, 2024Updated 2 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆49Aug 26, 2017Updated 8 years ago
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago