Alternatives and similar repositories for apb_uart_sv

Users that are interested in apb_uart_sv are comparing it to the libraries listed below

• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆19Updated 11 years ago
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆22Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆73Updated 5 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• haifengch / axi_interconnect
  ☆28Updated 6 months ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆25Updated last year
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆35Updated 8 years ago
• pulp-platform / apb
  APB Logic
  ☆22Updated 2 months ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆36Updated 7 months ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆31Updated 11 months ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆37Updated 3 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆42Updated 3 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆25Updated 6 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆54Updated 4 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆60Updated 6 months ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆17Updated 2 years ago
• aignacio / ahb_lite_bus
  AHB Bus lite v3.0
  ☆16Updated 6 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆28Updated 8 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆38Updated 9 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆35Updated 9 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆73Updated last year
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆32Updated 5 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago