tymonx / virtioLinks
Virtio implementation in SystemVerilog
☆47Updated 7 years ago
Alternatives and similar repositories for virtio
Users that are interested in virtio are comparing it to the libraries listed below
Sorting:
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 9 months ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆49Updated 3 weeks ago
- Ethernet switch implementation written in Verilog☆53Updated 2 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆113Updated this week
- Verilog Content Addressable Memory Module☆108Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- LIS Network-on-Chip Implementation☆31Updated 8 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆49Updated 9 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 6 months ago
- PCI Express controller model☆63Updated 2 years ago
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches