Virtio implementation in SystemVerilog
☆48Jan 23, 2018Updated 8 years ago
Alternatives and similar repositories for virtio
Users that are interested in virtio are comparing it to the libraries listed below
Sorting:
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Sep 16, 2020Updated 5 years ago
- A platform for emulating Virtio devices with FPGAs☆26Mar 31, 2021Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Aug 5, 2020Updated 5 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆286Nov 25, 2019Updated 6 years ago
- An FPGA-based NetTLP adapter☆27Mar 10, 2020Updated 5 years ago
- Distributed Accelerator OS☆64Apr 6, 2022Updated 3 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 8 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 8 years ago
- Network packet parser generator☆53Sep 11, 2020Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- ☆36Jan 21, 2021Updated 5 years ago
- ☆20Jan 31, 2026Updated last month
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 8 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- A collection of cryptographic algorthms implemented in SystemVerilog☆20Jun 7, 2018Updated 7 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- A library for PCIe Transaction Layer☆62Apr 27, 2022Updated 3 years ago
- A Programmable Hardware Architecture for Network Transport Logic☆36Oct 26, 2021Updated 4 years ago
- NVMe Controller featuring Hardware Acceleration☆101Jun 23, 2021Updated 4 years ago
- P4-14/16 Bluespec Compiler☆90Dec 26, 2017Updated 8 years ago
- This repo contains the Limago code☆92May 8, 2025Updated 9 months ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆24Nov 10, 2024Updated last year
- Flexible, high-performance TCP offload to SmartNICs using fine-grained parallelism☆60Feb 27, 2022Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated 3 weeks ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago
- Towards Hardware and Software Continuous Integration☆13Jun 8, 2020Updated 5 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Feb 22, 2018Updated 8 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- SystemVerilog Example Files☆11Jan 15, 2013Updated 13 years ago
- FPGA-based HyperLogLog Accelerator☆12Jul 13, 2020Updated 5 years ago