lite-david / cometLinks
RISC-V ISA based 32-bit processor written in HLS
☆16Updated 6 years ago
Alternatives and similar repositories for comet
Users that are interested in comet are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆76Updated last month
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ☆28Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆32Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago
- ☆64Updated 5 years ago
- Public release☆58Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- ☆79Updated 11 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- PYNQ Composabe Overlays☆73Updated last year
- Train and deploy LUT-based neural networks on FPGAs☆109Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- ☆71Updated 7 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- CNN accelerator☆28Updated 8 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated 11 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- ☆30Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago