lite-david / cometLinks
RISC-V ISA based 32-bit processor written in HLS
☆16Updated 6 years ago
Alternatives and similar repositories for comet
Users that are interested in comet are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 2 weeks ago
- ☆79Updated 11 years ago
- ☆28Updated 6 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- ☆71Updated 6 years ago
- ☆72Updated 2 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Public release☆58Updated 6 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆22Updated last year
- ☆63Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- CNN accelerator☆27Updated 8 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Train and deploy LUT-based neural networks on FPGAs☆102Updated last year
- PYNQ Composabe Overlays☆73Updated last year
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 8 years ago
- ☆30Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago