drom / atom-hide
Atom Hardware IDE
☆13Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for atom-hide
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- GUI editor for hardware description designs☆27Updated last year
- A padring generator for ASICs☆22Updated last year
- VHDL dependency analyzer☆22Updated 4 years ago
- sample VCD files☆36Updated 9 months ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆15Updated 4 months ago
- Docker Development Environment for SpinalHDL☆18Updated 3 months ago
- USB virtual model in C++ for Verilog☆28Updated last month
- Wishbone interconnect utilities☆37Updated 5 months ago
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- Python/Simulator integration using procedure calls☆9Updated 4 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- Library of reusable VHDL components☆25Updated 8 months ago
- Extended and external tests for Verilator testing☆15Updated last week
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆34Updated 3 years ago
- ☆13Updated 4 years ago
- RISC-V processor☆28Updated 2 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆11Updated 3 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Provides automation scripts for building BFMs☆16Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- VHDL Code for infrastructural blocks (designed for FPGA)☆12Updated 2 years ago
- A vhdl package for reading and writing bitmap files.☆11Updated 6 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 2 years ago
- Generate symbols from HDL components/modules☆20Updated last year
- A configurable USB 2.0 device core☆30Updated 4 years ago
- USB Full Speed PHY☆39Updated 4 years ago