Alternatives and similar repositories for BlobPlacement

Users that are interested in BlobPlacement are comparing it to the libraries listed below

• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆154Updated this week
• cuhk-eda / GCS-Timer
  ☆25Updated last month
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆60Updated 7 months ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆86Updated last year
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆77Updated 7 months ago
• cuhk-eda / cu-gr-2
  ☆48Updated 2 years ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆31Updated 2 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last month
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆76Updated last week
• NVlabs / Differentiable-Global-Router
  ☆22Updated last year
• ABKGroup / TritonRoute-WXL
  ☆35Updated 5 years ago
• zshi0616 / python-deepgate
  ☆27Updated last year
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆54Updated last year
• ABKGroup / ISPD26-Contest
  ISPD26 Contest: Post-Placement Buffering and Sizing
  ☆26Updated last week
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆39Updated 3 weeks ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆136Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆64Updated 7 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆108Updated last year
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆31Updated 3 years ago
• PKU-IDEA / MacroRank
  Official implementation of MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy (ASP-DAC 2023)
  ☆17Updated 2 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆42Updated 3 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆142Updated 2 years ago
• VidyaChhabria / ThermEDGe-and-IREDGe
  Encoder-decoder based generative networks for static and transient thermal analysis
  ☆23Updated 2 years ago
• zshi0616 / DeepGate2
  ☆31Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆75Updated last month
• NVlabs / INSTA
  ☆91Updated 7 months ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆14Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆61Updated last year
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆26Updated last year