pulp-platform / occamyLinks
A high-efficiency system-on-chip for floating-point compute workloads.
☆39Updated 6 months ago
Alternatives and similar repositories for occamy
Users that are interested in occamy are comparing it to the libraries listed below
Sorting:
- An energy-efficient RISC-V floating-point compute cluster.☆98Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated 2 weeks ago
- ☆73Updated last week
- The multi-core cluster of a PULP system.☆105Updated last week
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 7 months ago
- ☆52Updated last week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆107Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated 3 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆106Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- ☆59Updated this week
- PACoGen: Posit Arithmetic Core Generator☆75Updated 5 years ago
- Self checking RISC-V directed tests☆111Updated 2 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- high-performance RTL simulator☆172Updated last year
- Vector Acceleration IP core for RISC-V*☆181Updated 3 months ago
- ☆25Updated this week
- Open-source RTL logic simulator with CUDA acceleration☆201Updated this week
- CGRA framework with vectorization support.☆34Updated last week
- Pure digital components of a UCIe controller☆66Updated last month
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆87Updated 2 months ago
- The Task Parallel System Composer (TaPaSCo)☆111Updated 2 months ago
- ☆47Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- The specification for the FIRRTL language☆62Updated last week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year