bangonkali / sram
Simple sram controller in verilog.
☆32Updated 8 years ago
Alternatives and similar repositories for sram:
Users that are interested in sram are comparing it to the libraries listed below
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- ☆36Updated 9 years ago
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 7 months ago
- An implementation of the CORDIC algorithm in Verilog.☆93Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 3 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆32Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆82Updated 5 years ago
- Mathematical Functions in Verilog☆91Updated 4 years ago
- round robin arbiter☆72Updated 10 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆40Updated last year
- A Framework for Design and Verification of Image Processing Applications using UVM☆96Updated 7 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆152Updated 3 years ago