jdocampom / JPEG-DecoderLinks
Verilog Code for a JPEG Decoder
☆34Updated 7 years ago
Alternatives and similar repositories for JPEG-Decoder
Users that are interested in JPEG-Decoder are comparing it to the libraries listed below
Sorting:
- Implementation of the PCIe physical layer☆57Updated 4 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- ☆38Updated 10 years ago
- 异步FIFO的内部实现☆25Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- AXI Interconnect☆54Updated 4 years ago
- JPEG Encoder Verilog☆78Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- ☆17Updated 10 years ago
- UVM resource from github, run simulation use YASAsim flow☆31Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- AXI4 BFM in Verilog☆35Updated 8 years ago
- ☆31Updated 5 years ago
- ☆16Updated 6 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆69Updated last year
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- ☆34Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago