donpromax / ECC-Verilog-HDL-AutoGenerator
a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
☆11Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for ECC-Verilog-HDL-AutoGenerator
- verification of simple axi-based cache☆17Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- ☆16Updated last year
- ☆25Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- ☆33Updated 2 years ago
- ☆26Updated 5 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- A verilog implementation for Network-on-Chip☆66Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆30Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆47Updated 4 months ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 11 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- AXI Interconnect☆45Updated 3 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- ☆22Updated 5 years ago
- UART design in SV and verification using UVM and SV☆37Updated 4 years ago
- round robin arbiter☆67Updated 10 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆16Updated 3 years ago
- CORE-V MCU UVM Environment and Test Bench☆17Updated 3 months ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆24Updated 4 years ago
- SoC Based on ARM Cortex-M3☆25Updated 5 months ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- ☆67Updated 10 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆15Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆29Updated 2 years ago