donpromax / ECC-Verilog-HDL-AutoGeneratorLinks
a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
☆11Updated 5 years ago
Alternatives and similar repositories for ECC-Verilog-HDL-AutoGenerator
Users that are interested in ECC-Verilog-HDL-AutoGenerator are comparing it to the libraries listed below
Sorting:
- ☆29Updated 5 years ago
- ☆36Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- ☆62Updated 3 years ago
- ☆78Updated 10 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15☆13Updated 4 years ago
- ☆27Updated 5 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Sample UVM code for axi ram dut☆37Updated 3 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆40Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆34Updated 11 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- AXI4 BFM in Verilog☆33Updated 8 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆33Updated 3 years ago