a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.
☆11Dec 14, 2019Updated 6 years ago
Alternatives and similar repositories for ECC-Verilog-HDL-AutoGenerator
Users that are interested in ECC-Verilog-HDL-AutoGenerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 7 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆55Apr 29, 2015Updated 11 years ago
- Collect some IC specs for learning.☆26Jun 25, 2024Updated 2 years ago
- AXI4 to SRAM Interface☆13May 2, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Hamming ECC Encoder and Decoder to protect memories☆37Jan 28, 2025Updated last year
- 卡内基梅隆大学 CSAPP3e 原书与哔哩哔哩视频课件☆12May 13, 2022Updated 4 years ago
- 计算机网络书籍☆16May 14, 2022Updated 4 years ago
- ☆17Jun 5, 2024Updated 2 years ago
- This repository contains the code for this paper: Chiplet-Gym: An RL-based Optimization Framework for Chiplet-based AI Accelerator☆25Sep 28, 2024Updated 2 years ago
- Community Windows desktop client for Step Code☆27Updated this week
- Parallel_Computer_Architecture经典书籍☆20May 13, 2022Updated 4 years ago
- Fully automatic brain tumor segmentation using the Modified 3DUNet architecture for Brats 2020 Challenge.☆16Jun 29, 2021Updated 5 years ago
- ☆16Mar 19, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- P4_16 reference compiler☆23Dec 30, 2025Updated 10 months ago
- Feature extraction for overall survival prediction in BraTS 2019 challenge☆11Jan 17, 2021Updated 5 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- ☆10Jan 30, 2017Updated 9 years ago
- ☆20Aug 22, 2022Updated 4 years ago
- This is a SystemVerilog HDL implementation of Karatsuba multiplier.☆11Jul 8, 2020Updated 6 years ago
- 🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and in…☆19Sep 27, 2026Updated last month
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 7 years ago
- X86 Instruction Profiler☆13May 19, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Try to implement and test CVPR 2019 paper "Res2Net: A New Multi-scale Backbone Architecture" in PyTorch.☆17Jun 7, 2020Updated 6 years ago
- 国科大软件安全原理作业☆25Oct 27, 2020Updated 6 years ago
- C++ code and MATLAB utilities for loading patterns onto TI DLP Digital Micromirror Device (DMD)☆14Dec 19, 2020Updated 5 years ago
- 计算机组织与设计硬件软件接口 原书与伯克利大学哔哩哔哩视频课件☆24May 13, 2022Updated 4 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- ☆16Dec 3, 2020Updated 5 years ago
- 一个Android SMALI 文件翻译为Java代码的工具☆16Sep 1, 2019Updated 7 years ago
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code（使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 3 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- LC6500DMD python control☆11Nov 15, 2016Updated 9 years ago
- ☆17Aug 4, 2014Updated 12 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- 一个为华南农业大学（SCAU）教务系统量身打造的专业级油猴脚本，旨在全自动化抢课流程。功能包括：批量课程捕获、定时发包、自动重试、智能时间识别等。☆14Jun 12, 2025Updated last year
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆15Apr 11, 2023Updated 3 years ago
- Unet with Attention☆14Feb 19, 2020Updated 6 years ago
- This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction schedulin…☆19May 14, 2021Updated 5 years ago
Are these results useful?