Verilog implementation of various types of CPUs
☆76Sep 27, 2019Updated 6 years ago
Alternatives and similar repositories for Verilog-Harvard-CPU
Users that are interested in Verilog-Harvard-CPU are comparing it to the libraries listed below
Sorting:
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- 𝐈𝐬𝐥𝐚𝐦𝐢𝐜𝐓𝐫𝐚𝐧𝐬𝐥𝐚𝐭𝐨𝐫 is an automated solution designed to translate 𝐇𝐚𝐝𝐢𝐭𝐡𝐬 into multiple languages using the power …☆11Jan 17, 2025Updated last year
- Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog☆20Mar 11, 2021Updated 4 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- 🍁🍂🍃 A C# implementation of the 65el02 CPU.☆10Oct 12, 2021Updated 4 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆11May 17, 2024Updated last year
- Design of a 16-Bit CPU using Verilog☆48Jun 11, 2019Updated 6 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- My PhD manuscript LaTeX code and the slides for the defense☆11Feb 2, 2022Updated 4 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 6 years ago
- ☆13Jan 7, 2025Updated last year
- our code☆33Jun 11, 2021Updated 4 years ago
- An experimental raytracer in LaTeX☆30Nov 29, 2021Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Mar 28, 2025Updated 11 months ago
- High Throughput Image Filters on FPGAs☆14Oct 17, 2017Updated 8 years ago
- Simple cache design implementation in verilog☆55Nov 20, 2023Updated 2 years ago
- Presentation for pt-three-ways - a CppCon 2019 presentation☆14Jan 23, 2025Updated last year
- An almost empty chisel project as a starting point for hardware design☆35Jan 27, 2025Updated last year
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- A Numpy implementation of a Generative Adversarial Network.☆17Sep 4, 2020Updated 5 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 5 years ago
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- JapaneseArabic Dictionary (日本語・アラビア語辞書) قاموس اللغة اليابانية والعربية (Yomitan)☆17May 20, 2025Updated 9 months ago
- The open source web portal for EPITA websites and projects.☆44Feb 4, 2026Updated last month
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- Verification IP for SPI protocol☆20Jul 23, 2020Updated 5 years ago
- ☆25Aug 9, 2022Updated 3 years ago
- RISC-V instruction set extensions for SM4 block cipher☆21Mar 6, 2020Updated 6 years ago
- Library for structured fuzzing of ASN.1 DER/BER☆19Sep 6, 2022Updated 3 years ago
- ☆18Aug 8, 2017Updated 8 years ago
- Verification IP for UART protocol☆23Aug 3, 2020Updated 5 years ago